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CY7C66013 CY7C66113
Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
Cypress Semiconductor Corporation Document #: 38-08024 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised March 6, 2003
CY7C66013 CY7C66113
TABLE OF CONTENTS 1.0 FEATURES ...................................................................................................................................... 6 2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 7 2.1 GPIO ........................................................................................................................................... 7 2.2 DAC ............................................................................................................................................ 7 2.3 Clock ........................................................................................................................................... 7 2.4 Memory ....................................................................................................................................... 7 2.5 Power-on Reset, Watchdog, and Free-running Time ................................................................. 7 2.6 I2C and HAPI Interface ............................................................................................................... 7 2.7 Timer ........................................................................................................................................... 7 2.8 Interrupts ..................................................................................................................................... 8 2.9 USB ............................................................................................................................................. 8 3.0 PIN CONFIGURATIONS ................................................................................................................ 10 4.0 PRODUCT SUMMARY TABLES ................................................................................................... 11 4.1 Pin Assignments ....................................................................................................................... 11 4.2 I/O Register Summary .............................................................................................................. 11 4.3 Instruction Set Summary ........................................................................................................... 13 5.0 PROGRAMMING MODEL .............................................................................................................. 14 5.1 14-bit Program Counter (PC) .................................................................................................... 14
5.1.1 Program Memory Organization ..................................................................................................... 15
5.2 8-Bit Accumulator (A) ................................................................................................................ 16 5.3 8-Bit Temporary Register (X) .................................................................................................... 16 5.4 8-Bit Program Stack Pointer (PSP) ........................................................................................... 16
5.4.1 Data Memory Organization ............................................................................................................. 16
5.5 8-Bit Data Stack Pointer (DSP) ................................................................................................. 16 5.6 Address Modes ......................................................................................................................... 17
5.6.1 Data (Immediate) ............................................................................................................................ 17 5.6.2 Direct ............................................................................................................................................... 17 5.6.3 Indexed ........................................................................................................................................... 17
6.0 CLOCKING ..................................................................................................................................... 17 7.0 RESET ............................................................................................................................................ 18 7.1 Power-on Reset ........................................................................................................................ 18 7.2 Watchdog Reset ....................................................................................................................... 18 8.0 SUSPEND MODE ........................................................................................................................... 19 9.0 GENERAL-PURPOSE I/O (GPIO) PORTS .................................................................................... 19 9.1 GPIO Configuration Port ........................................................................................................... 20 9.2 GPIO Interrupt Enable Ports ..................................................................................................... 21 10.0 DAC PORT ................................................................................................................................... 22 10.1 DAC Isink Registers ................................................................................................................ 23 10.2 DAC Port Interrupts ................................................................................................................. 23 11.0 12-BIT FREE-RUNNING TIMER .................................................................................................. 24 12.0 I2C AND HAPI CONFIGURATION REGISTER ............................................................................ 24 13.0 I2C-COMPATIBLE CONTROLLER .............................................................................................. 25 14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................ 27 15.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................ 28
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TABLE OF CONTENTS (continued) 16.0 INTERRUPTS ............................................................................................................................... 29 16.1 Interrupt Vectors ..................................................................................................................... 30 16.2 Interrupt Latency ..................................................................................................................... 31 16.3 USB Bus Reset Interrupt ......................................................................................................... 31 16.4 Timer Interrupt ........................................................................................................................ 31 16.5 USB Endpoint Interrupts ......................................................................................................... 32 16.6 USB Hub Interrupt ................................................................................................................... 32 16.7 DAC Interrupt .......................................................................................................................... 32 16.8 GPIO/HAPI Interrupt ............................................................................................................... 32 16.9 I2C Interrupt ............................................................................................................................. 33 17.0 USB OVERVIEW .......................................................................................................................... 33 17.1 USB Serial Interface Engine ................................................................................................... 33 17.2 USB Enumeration ................................................................................................................... 33 18.0 USB HUB ..................................................................................................................................... 34 18.1 Connecting/Disconnecting a USB Device ............................................................................... 34 18.2 Enabling/Disabling a USB Device ........................................................................................... 35 18.3 Hub Downstream Ports Status and Control ............................................................................ 35 18.4 Downstream Port Suspend and Resume ................................................................................ 37 18.5 USB Upstream Port Status and Control .................................................................................. 38 19.0 USB SIE OPERATION ................................................................................................................. 39 19.1 USB Device Addresses ........................................................................................................... 39 19.2 USB Device Endpoints ............................................................................................................ 39 19.3 USB Control Endpoint Mode Registers ................................................................................... 40 19.4 USB Non-Control Endpoint Mode Registers ........................................................................... 41 19.5 USB Endpoint Counter Registers ........................................................................................... 41 19.6 Endpoint Mode/Count Registers Update and Locking Mechanism ......................................... 42 20.0 USB MODE TABLES ................................................................................................................... 44 21.0 REGISTER SUMMARY ................................................................................................................ 48 22.0 SAMPLE SCHEMATIC ................................................................................................................ 51 23.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 52 24.0 ELECTRICAL CHARACTERISTICS ............................................................................................ 52 25.0 SWITCHING CHARACTERISTICS (fOSC = 6.0 MHz) ...................................................................................... 53 26.0 ORDERING INFORMATION ........................................................................................................ 55 27.0 PACKAGE DIAGRAMS ............................................................................................................... 56
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LIST OF FIGURES Figure 5-1. Program Memory Space with Interrupt Vector Table ......................................................... 15 Figure 6-1. Clock Oscillator On-Chip Circuit ......................................................................................... 17 Figure 7-1. Watchdog Reset ................................................................................................................. 18 Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................. 19 Figure 9-2. Port 0 Data ......................................................................................................................... 20 Figure 9-3. Port1 Data .......................................................................................................................... 20 Figure 9-4. Port 2 Data ......................................................................................................................... 20 Figure 9-5. Port 3 Data ......................................................................................................................... 20 Figure 9-6. GPIO Configuration Register .............................................................................................. 20 Figure 9-7. Port 0 Interrupt Enable ....................................................................................................... 21 Figure 9-8. Port 1 Interrupt Enable ....................................................................................................... 22 Figure 9-9. Port 2 Interrupt Enable ....................................................................................................... 22 Figure 9-10. Port 3 Interrupt Enable ..................................................................................................... 22 Figure 10-1. Block Diagram of a DAC Pin ............................................................................................ 22 Figure 10-2. DAC Port Data .................................................................................................................. 23 Figure 10-3. DAC Sink Register ........................................................................................................... 23 Figure 10-4. DAC Port Interrupt Enable ................................................................................................ 23 Figure 10-5. DAC Port Interrupt Polarity ............................................................................................... 23 Figure 11-3. Timer Block Diagram ........................................................................................................ 24 Figure 11-1. Timer LSB Register .......................................................................................................... 24 Figure 11-2. Timer MSB Register ......................................................................................................... 24 Figure 12-1. HAPI/I2C Configuration Register ...................................................................................... 24 Figure 13-1. I2C Data Register .............................................................................................................. 25 Figure 13-2. I2C Status and Control Register ....................................................................................... 25 Figure 15-1. Processor Status and Control Register ............................................................................ 28 Figure 16-1. Global Interrupt Enable Register ...................................................................................... 29 Figure 16-2. USB Endpoint Interrupt Enable Register .......................................................................... 29 Figure 16-3. Interrupt Controller Function Diagram .............................................................................. 30 Figure 16-4. GPIO Interrupt Structure .................................................................................................. 32 Figure 18-1. Hub Ports Connect Status ................................................................................................ 34 Figure 18-2. Hub Ports Speed .............................................................................................................. 35 Figure 18-3. Hub Ports Enable Register ............................................................................................... 35 Figure 18-4. Hub Downstream Ports Control Register ......................................................................... 36 Figure 18-5. Hub Ports Force Low Register ......................................................................................... 36 Figure 18-6. Hub Ports Force Low Register ......................................................................................... 36 Figure 18-7. Hub Ports SE0 Status Register ........................................................................................ 36 Figure 18-8. Hub Ports Data Register .................................................................................................. 37 Figure 18-9. Hub Ports Suspend Register ............................................................................................ 37 Figure 18-10. Hub Ports Resume Status Register ............................................................................... 37 Figure 18-11. USB Status and Control Register ................................................................................... 38 Figure 19-1. USB Device Address Registers ........................................................................................ 39 Figure 19-2. USB Device Endpoint Zero Mode Registers .................................................................... 40 Figure 19-3. USB Non-Control Device Endpoint Mode Registers ........................................................ 41 Figure 19-4. USB Endpoint Counter Registers ..................................................................................... 41 Figure 19-5. Token/Data Packet Flow Diagram .................................................................................... 43 Figure 22-1. Sample Schematic ........................................................................................................... 51 Figure 25-1. Clock Timing ..................................................................................................................... 54 Figure 25-2. USB Data Signal Timing ................................................................................................... 54 Figure 25-3. HAPI Read by External Interface from USB Microcontroller ............................................ 54 Figure 25-4. HAPI Write by External Device to USB Microcontroller .................................................... 55
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LIST OF TABLES Table 4-1. Pin Assignments .................................................................................................................. 11 Table 4-2. I/O Register Summary ......................................................................................................... 11 Table 4-3. Instruction Set Summary ..................................................................................................... 13 Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity .............................................. 21 Table 12-1. HAPI Port Configuration .................................................................................................... 25 Table 12-2. I2C Port Configuration ........................................................................................................ 25 Table 13-1. I2C Status and Control Register Bit Definitions .................................................................. 26 Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions ............................................................. 27 Table 16-1. Interrupt Vector Assignments ............................................................................................ 31 Table 18-1. Control Bit Definition for Downstream Ports ...................................................................... 36 Table 18-2. Control Bit Definition for Upstream Port ............................................................................ 39 Table 19-1. Memory Allocation for Endpoints ..................................................................................... 40 Table 20-1. USB Register Mode Encoding ........................................................................................... 44 Table 20-2. Decode Table for Table 20-3: "Details of Modes for Differing Traffic Conditions" ............. 45 Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) 46
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1.0 Features
* Full-speed USB peripheral microcontroller with an integrated USB hub -- Well-suited for USB compound devices such as a keyboard hub function * 8-bit USB optimized microcontroller -- Harvard architecture -- 6-MHz external clock source -- 12-MHz internal CPU clock -- 48-MHz internal Hub clock * Internal memory -- 256 bytes of RAM -- 8 KB of PROM (CY7C66013, CY7C66113) * Integrated Master/Slave I2C-compatible controller (100 kHz) enabled through General-purpose I/O (GPIO) pins * Hardware-assisted Parallel Interface (HAPI) for data transfer to external devices * I/O ports -- Three GPIO ports (Port 0 to 2) capable of sinking 8 mA per pin (typical) -- An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs -- Higher current drive achievable by connecting multiple GPIO pins together to drive a common output -- Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs -- A Digital-to-Analog Conversion (DAC) port with programmable current sink outputs is available on the CY7C66113 device * * * * -- Maskable interrupts on all I/O pins 12-bit free-running timer with one microsecond clock ticks Watchdog Timer (WDT) Internal Power-on Reset (POR) USB Specification compliance -- Conforms to USB Specification, Version 1.1 -- Conforms to USB HID Specification, Version 1.1 -- Supports one or two device addresses with up to five user-configured endpoints * Up to two 8-byte control endpoints * Up to four 8-byte data endpoints * Up to two 32-byte data endpoints -- Integrated USB transceivers -- Supports four downstream USB ports -- GPIO pins can provide individual power control outputs for each downstream USB port * * * * * * -- GPIO pins can provide individual port over current inputs for each downstream USB port Improved output drivers to reduce electromagnetic interference (EMI) Operating voltage from 4.0V - 5.5V DC Operating temperature from 0 - 70C CY7C66013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages CY7C66113 available in 56-pin SSOP (-PVC) packages Industry-standard programmer support
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2.0 Functional Overview
The CY7C66013 and CY7C66113 are compound devices with a full-speed USB microcontroller in combination with a USB hub. Each device is well-suited for combination peripheral functions with hubs, such as a keyboard hub function. The eight-bit one-time-programmable microcontroller with a 12-Mbps USB Hub supports as many as four downstream ports.
2.1
GPIO
The CY7C66013 features 29 GPIO pins to support USB and other applications. The I/O pins are grouped into four ports (P0[7:0], P1[7:0], P2[7:0], P3[4:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Ports 0 to 2 are rated at 8 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same "GPIO" interrupt vector. The CY7C66113 has 31 GPIO pins (P0[7:0], P1[7:0], P2[7:0], P3[6:0]).
2.2
DAC
The CY7C66113 have an additional port P4[7:0] that features an additional eight programmable sink current I/O pins (DAC). Every DAC pin includes an integrated 14-k pull-up resistor. When a `1' is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull-up resistor. When a `0' is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a `1' to the pin. The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits DAC[1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits DAC[7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable.
2.3
Clock
The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcontroller.
2.4
Memory
The CY7C66013 and CY7C66113 have 8 KB of PROM.
2.5
Power-on Reset, Watchdog, and Free-running Time
These parts include POR logic, a WDT, and a 12-bit free-running timer. The POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The WDT is used to ensure that the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.
2.6
I2C and HAPI Interface
The microcontroller can communicate with external electronics through the GPIO pins. An I2C-compatible interface accommodates a 100-kHz serial link with an external device. There is also a Hardware-assisted Parallel Interface (HAPI) which can be used to transfer data to an external device.
2.7
Timer
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-s and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read.
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2.8 Interrupts
The microcontroller supports eleven maskable interrupts in the vectored interrupt controller. Interrupt sources include the 128-s (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the USB hub, the DAC port, the GPIO ports, and the I2C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW `0' to HIGH `1.' The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge (`0' to `1') or falling edge (`1' to `0').
2.9
USB
The CY7C66013 and CY7C66113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows power-management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power-management pins, or providing power management for each port with four pairs of power-management pins.
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Logic Block Diagram
6-MHz crystal USB Transceiver
D+[0] Upstream D-[0] USB Port
PLL USB Transceiver
D+[1] D-[1]
48 MHz Clock Divider 12 MHz PROM 8 KB 8-bit Bus USB SIE
12-MHz 8-bit CPU Repeater
USB Transceiver
D+[2] D-[2]
USB Transceiver
D+[3] D-[3]
RAM 256 byte
Interrupt Controller
USB Transceiver
D+[4] D-[4]
Downstream USB Ports
6 MHz 12-bit Timer
GPIO PORT 0
P0[0] P0[7]
Power management under firmware control using GPIO pins
Watchdog Timer
GPIO PORT 1
P1[0] P1[7]
Power-On Reset
GPIO/ HAPI PORT 2
P2[0:1,7] P2[2]; Latch_Empty P2[3]; Data_Ready P2[4]; STB P2[5]; OE P2[6]; CS P3[0] P3[4]
GPIO PORT 3 GPIO PORT 3 DAC PORT
High Current Outputs
P3[5] Additional High Current P3[6] Outputs DAC[0] DAC[7] CY7C66113 only SCLK SDATA
I2C Interface
*I2C-compatible interface enabled by firmware through P2[1:0] or P1[1:0]
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3.0 Pin Configurations
TOP VIEW CY7C66013 48-pin PDIP/SSOP
XTALOUT XTALIN VREF P1[3] P1[5] P1[7] P3[1] D+[0] D-[0] P3[3] GND D+[1] D-[1] P2[1] D+[2] D-[2] P2[3] P2[5] P2[7] GND P0[7] P0[5] P0[3] P0[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] D-[3] D+[3] P3[2] GND P3[4] D-[4] D+[4] P2[0] P2[2] GND P2[4] P2[6] VPP P0[0] P0[2] P0[4] P0[6] XTALOUT XTALIN VREF P1[3] P1[5] P1[7] P3[1] D+[0] D-[0] P3[3] GND P3[5] D+[1] D-[1] P2[1] D+[2] D-[2] P2[3] P2[5] P2[7] DAC[7] P0[7] P0[5] P0[3] P0[1] DAC[5] DAC[3] DAC[1]
CY7C66113 56-pin SSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VCC P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] D-[3] D+[3] P3[2] P3[4] D-[4] D+[4] P3[6] P2[0] P2[2] GND P2[4] P2[6] DAC[0] VPP P0[0] P0[2] P0[4] P0[6] DAC[2] DAC[4] DAC[6]
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4.0
4.1
Product Summary Tables
Pin Assignments
Table 4-1. Pin Assignments Name
D+[0], D-[0] D+[1], D-[1] D+[2], D-[2] D+[3], D-[3] D+[4], D-[4] P0[7:0] P1[7:0] P2[7:0] P3[6:0] DAC[7:0] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
8, 9
48-Pin
8, 9 12, 13 15, 16 40, 41 35, 36 21, 25, 22, 26, 23, 27, 24, 28 6, 43, 5, 44, 4, 45, 47, 46 19, 30, 18, 31, 17, 33, 14, 34
56-Pin
13, 14 16, 17 48, 49 44, 45
Description Upstream port, USB differential data. Downstream port 1, USB differential data. Downstream port 2, USB differential data. Downstream port 3, USB differential data. Downstream port 4, USB differential data.
22, 32, 23, 33, GPIO Port 0. 24, 34, 25, 35 6, 51, 5, 52, 4, GPIO Port 1. 53, 55, 54 20, 38, 19, 39, GPIO Port 2. 18, 41, 15, 42
37, 10, 39, 7, 42 43, 12, 46, 10, GPIO Port 3, capable of sinking 12 mA (typical). 47, 7, 50 n/a 21, 29, 26, 30, Digital to Analog Converter (DAC) Port with programmable current 27, 31, 28, 37 sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7:2] have a programmable sink current range of 0.2 to 1.0 mA typical.
XTALIN XTALOUT VPP VCC GND VREF IN IN OUT 2 1 29 48 11, 20, 32, 38 3 2 1 36 56 11, 40 3
6-MHz crystal or external clock input. 6-MHz crystal out. Programming voltage supply, tie to ground during normal operation. Voltage supply. Ground. External 3.3V supply voltage for the differential data output buffers and the D+ pull-up.
4.2
I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X. All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with `0.' Table 4-2. I/O Register Summary Register Name Port 0 Data Port 1 Data Port 2 Data Port 3 Data Port 0 Interrupt Enable Port 1 Interrupt Enable Port 2 Interrupt Enable Port 3 Interrupt Enable GPIO Configuration I/O Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
Read/Write
R/W R/W R/W R/W W W W W R/W
Function GPIO Port 0 Data GPIO Port 1 Data GPIO Port 2 Data GPIO Port 3 Data Interrupt Enable for Pins in Port 0 Interrupt Enable for Pins in Port 1 Interrupt Enable for Pins in Port 2 Interrupt Enable for Pins in Port 3 GPIO Port Configurations
Page
20 20 20 20 21 22 22 22 20
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Table 4-2. I/O Register Summary (continued) Register Name HAPI and I2C Configuration USB Device Address A EP A0 Counter Register EP A0 Mode Register EP A1 Counter Register EP A1 Mode Register EP A2 Counter Register EP A2 Mode Register USB Status & Control Global Interrupt Enable Endpoint Interrupt Enable Interrupt Vector Timer (LSB) Timer (MSB) WDT Clear I2C I2C Control & Status Data I/O Address
0x09 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x1F 0x20 0x21 0x23 0x24 0x25 0x26 0x28 0x29 0x30 0x31 0x32 0x38-0x3F 0x40 0x41 0x42 0x43 0x44 0x48 0x49 0x4A 0x4B 0x4D 0x4E 0x4F 0x50 0x51 0xFF
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R W R/W R/W R/W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W
Function HAPI Width and I2C Position Configuration USB Device Address A USB Address A, Endpoint 0 Counter USB Address A, Endpoint 0 Configuration USB Address A, Endpoint 1 Counter USB Address A, Endpoint 1 Configuration USB Address A, Endpoint 2 Counter USB Address A, Endpoint 2 Configuration USB Upstream Port Traffic Status and Control Global Interrupt Enable USB Endpoint Interrupt Enables Pending Interrupt Vector Read/Clear Lower 8 Bits of Free-running Timer (1 MHz) Upper 4 Bits of Free-running Timer Watchdog Timer Clear I2 C I2 C Status and Control Data
Page
24 39 41 40 41 41 41 41 38 29 29 31 24 24 18 25 25 23 23 23 23
DAC Data DAC Interrupt Enable DAC Interrupt Polarity DAC Isink USB Device Address B EP B0 Counter Register EP B0 Mode Register EP B1 Counter Register EP B1 Mode Register Hub Port Connect Status Hub Port Enable Hub Port Speed Hub Port Control (Ports [4:1]) Hub Port Suspend Hub Port Resume Status Hub Ports SE0 Status Hub Ports Data Hub Downstream Force Low Processor Status & Control
DAC Data Interrupt Enable for each DAC Pin Interrupt Polarity for each DAC Pin Input Sink Current Control for each DAC Pin USB Address B, Endpoint 0 Counter USB Address B, Endpoint 0 Configuration, or USB Address A, Endpoint 3 in 5-endpoint mode USB Address B, Endpoint 1 Counter USB Address B, Endpoint 1 Configuration, or USB Address A, Endpoint 4 in 5-endpoint mode Hub Downstream Port Connect Status Hub Downstream Ports Enable Hub Downstream Ports Speed Hub Downstream Ports Control Hub Downstream Port Suspend Control Hub Downstream Ports Resume Status Hub Downstream Ports SE0 Status Hub Downstream Ports Differential data Hub Downstream Ports Force LOW Microprocessor Status and Control Register
USB Device Address B (not used in 5-endpoint mode) 39
41 40 41 41 34 35 35 36 37 37 36 37 36 28
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4.3 Instruction Set Summary
Refer to the CYASM Assembler User's Guide for more details. Table 4-3. Instruction Set Summary MNEMONIC HALT ADD A,expr ADD A,[expr] ADD A,[X+expr] ADC A,expr ADC A,[expr] ADC A,[X+expr] SUB A,expr SUB A,[expr] SUB A,[X+expr] SBB A,expr SBB A,[expr] SBB A,[X+expr] OR A,expr OR A,[expr] OR A,[X+expr] AND A,expr AND A,[expr] AND A,[X+expr] XOR A,expr XOR A,[expr] XOR A,[X+expr] CMP A,expr CMP A,[expr] CMP A,[X+expr] MOV A,expr MOV A,[expr] MOV A,[X+expr] MOV X,expr MOV X,[expr] reserved XPAGE MOV A,X MOV X,A MOV PSP,A CALL JMP CALL JZ JNZ addr addr addr addr addr data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct operand opcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 40 41 60 50 - 5F 80-8F 90-9F A0-AF B0-BF 4 4 4 4 10 5 10 5 5 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 5 7 8 4 5 6 4 5 cycles MNEMONIC NOP INC A INC X INC [expr] INC [X+expr] DEC A DEC X DEC [expr] DEC [X+expr] IORD expr IOWR expr POP A POP X PUSH A PUSH X SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] CPL ASL ASR RLC RRC RET DI EI RETI JC JNC JACC INDEX addr addr addr addr direct index direct index direct index direct index index acc x direct index acc x direct index address address operand opcode 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 70 72 73 C0-CF D0-DF E0-EF F0-FF 4 4 4 7 8 4 4 7 8 5 5 4 4 5 5 5 5 5 6 7 8 7 8 7 8 6 4 4 4 4 4 8 4 4 8 5 5 7 14 cycles
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5.0
5.1
Programming Model
14-bit Program Counter (PC)
The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C66x13 architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Section 16.1, Interrupt Vectors, on page 30). The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte "page" of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly. The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.
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5.1.1 Program Memory Organization
after reset 14-bit PC Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A
Program execution begins here after a reset USB Bus Reset interrupt vector 128-s timer interrupt vector 1.024-ms timer interrupt vector USB address A endpoint 0 interrupt vector USB address A endpoint 1 interrupt vector USB address A endpoint 2 interrupt vector USB address B endpoint 0 interrupt vector USB address B endpoint 1 interrupt vector Hub interrupt vector DAC interrupt vector GPIO interrupt vector I2C interrupt vector Program Memory begins here
0x1FDF
8 KB (-32) PROM ends here (CY7C66013, CY7C66113)
Figure 5-1. Program Memory Space with Interrupt Vector Table
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5.2 8-Bit Accumulator (A)
The accumulator is the general-purpose register for the microcontroller.
5.3
8-Bit Temporary Register (X)
The "X" register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information.
5.4
8-Bit Program Stack Pointer (PSP)
During a reset, the Program Stack Pointer (PSP) is set to 0x00 and "grows" upward from this address. The PSP may be set by firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control. The PSP is not readable by the firmware. During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the PSP, then the PSP is incremented. The second byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program counter and flags on the program "stack" and increment the PSP by two. The Return From Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the PSP. The PSP is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The overall effect is to restore the program counter and flags from the program stack, decrement the PSP by two, and reenable interrupts. The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two. 5.4.1 Data Memory Organization
The CY7C66x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack, and user variables areas could be located.
After reset 8-bit DSP (Move DSP[1]) 8-bit PSP Address 0x00
Program Stack Growth
8-bit DSP
user selected
Data Stack Growth User variables
USB FIFO space for up to two Addresses and five endpoints[2]
0xFF
5.5
8-Bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs.
Notes: 1. Refer to Section 5.5 for a description of DSP. 2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 19-1.
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For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in Section 19.2. Example assembly instructions to do this with two device addresses (FIFOs begin at 0xD8) are shown below: MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register.
5.6
Address Modes
The CY7C66013 and CY7C66113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate)
"Data" address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xD8: * MOV A, 0D8h. This instruction requires two bytes of code where the first byte identifies the "MOV A" instruction with a data operand as the second byte. The second byte of the instruction is the constant "0xD8". A constant may be referred to by name if a prior "EQU" statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above: * DSPINIT: EQU 0D8h * MOV A, DSPINIT. 5.6.2 Direct
"Direct" address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10: * MOV A, [10h]. Normally, variable names are assigned to variable addresses using "EQU" statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above: * buttons: EQU 10h * MOV A, [buttons]. 5.6.3 Indexed
"Indexed" address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the "X" register. Normally, the constant is the "base" address of an array of data and the X register contains an index that indicates which element of the array is actually addressed: * array: EQU 10h * MOV X, 3 * MOV A, [X+array]. This would have the effect of loading A with the fourth element of the SRAM "array" that begins at address 0x10. The fourth element would be at address 0x13.
6.0
Clocking
XTALOUT (pin 1)
XTALIN (pin 2) 30 pF
To Internal PLL 30 pF
Figure 6-1. Clock Oscillator On-Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL. The two internal 30-pF load caps appear in series to the external crystal and would be equivalent to a 15-pF Document #: 38-08024 Rev. *A Page 17 of 58
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load. Therefore, the crystal must have a required load capacitance of about 15-18 pF. A ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with these parts. An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.
7.0
Reset
The CY7C66x13 supports two resets: POR and a Watchdog Reset (WDR). Each of these resets causes: * all registers to be restored to their default states * the USB device addresses to be set to 0 * all interrupts to be disabled * the PSP and DSP to be set to memory address 0x00. The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 15.0. Bits 4 and 6 are used to record the occurrence of POR and WDR, respectively. Firmware can interrogate these bits to determine the cause of a reset. Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware reset handler should configure the hardware before the "main" loop of code. Attempting to execute a RET or RETI in the firmware reset handler causes unpredictable execution results.
7.1
Power-on Reset
When VCC is first applied to the chip, the POR signal is asserted and the CY7C66x13 enters a "semi-suspend" state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator and all other blocks of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid VCC level is reached and that the internal PLL has time to stabilize before full operation begins. When the VCC has risen above approximately 2.5V, and the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream port. The 95 ms provides time for VCC to stabilize at a valid operating voltage before the chip executes code. If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command. The POR signal is asserted whenever VCC drops below approximately 2.5V, and remains asserted until VCC rises above this level again. Behavior is the same as described above.
7.2
Watchdog Reset
The WDR occurs when the internal WDT rolls over. Writing any value to the write-only Watchdog Restart Register at address 0x26 clears the timer. The timer rolls over and WDR occurs if it is not cleared within tWATCH (8 ms minimum) of the last clear. Bit 6 of the Processor Status and Control Register is set to record this event (the register contents are set to 010X0001 by the WDR). A WDT Reset lasts for 2 ms, after which the microcontroller begins execution at ROM address 0x0000. tWATCH 2 ms
Last write to WDT Register
No write to WDT register, so WDR goes HIGH
Execution begins at Reset Vector 0x0000
Figure 7-1. Watchdog Reset The USB transmitter is disabled by a WDR because the USB Device Address Registers are cleared (see Section 19.1). Otherwise, the USB Controller would respond to all address 0 transactions.
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It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. If a firmware interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored if the POR (bit 3 of register 0xFF) bit is set.
8.0
Suspend Mode
The CY7C66x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register. All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL, as well as the free-running and WDTs, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity at a USB upstream or downstream port wakes the part from suspend. The Run bit in the Processor Status and Control Register must be set to resume a part out of suspend. The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend mode before servicing any interrupt requests. The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at VCC or Gnd. This also applies to internal port pins that may not be bonded in a particular package. Typical code for entering suspend is shown below: ... ... mov a, 09h iowr FFh nop ... ; All GPIO set to low-power state (no floating pins) ; Enable GPIO interrupts if desired for wake-up ; Set suspend and run bits ; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt) ; This executes before any ISR ; Remaining code for exiting suspend routine.
9.0
General-purpose I/O (GPIO) Ports
GPIO CFG OE
VCC
mode 2-bits Q1 Data Out Latch Control Q2
Internal Data Bus Port Write
14 k GPIO PIN Q3*
Port Read
Data In Latch Control
Reg_Bit STRB
(Latch is Transparent except in HAPI mode)
Data Interrupt Latch
Interrupt Enable
Interrupt Controller
*Port 0,1,2: Low Isink Port 3: High Isink
Figure 9-1. Block Diagram of a GPIO Pin
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There are up to 31 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[6:0]) for the hardware interface. The number of GPIO pins changes based on the package type of the chip. Each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Port 3 offers a higher current drive, with typical current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset.
Port 0 Data Bit # Bit Name Read/Write Reset 7 P0.7 R/W 1 6 P0.6 R/W 1 5 P0.5 R/W 1 4 P0.4 R/W 1 3 P0.3 R/W 1 2 P0.2 R/W 1 1 P0.1 R/W 1 ADDRESS 0x00 0 P0.0 R/W 1
Figure 9-2. Port 0 Data
Port 1 Data Bit # Bit Name Read/Write Reset 7 P1.7 R/W 1 6 P1.6 R/W 1 5 P1.5 R/W 1 4 P1.4 R/W 1 3 Reserved R/W 1 2 P1.2 R/W 1 1 P1.1 R/W 1 ADDRESS 0x01 0 P1.0 R/W 1
Figure 9-3. Port1 Data
Port 2 Data Bit # Bit Name Read/Write Reset 7 P2.7 R/W 1 6 P2.6 R/W 1 5 P2.5 R/W 1 4 P2.4 R/W 1 3 P2.3 R/W 1 2 Reserved R/W 1 1 Reserved R/W 1 ADDRESS 0x02 0 Reserved R/W 1
Figure 9-4. Port 2 Data
Port 3 Data Bit # Bit Name Read/Write Reset 7 Reserved R/W 1 6 Reserved R/W 1 5 Reserved R/W 1 4 Reserved R/W 1 3 Reserved R/W 1 2 Reserved R/W 1 1 P3.1 R/W 1 ADDRESS 0x03 0 P3.0 R/W 1
Figure 9-5. Port 3 Data Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB specifications. If a `1' is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a `0.' Notice that the CY7C66013 always requires that P3[7:5] be written with a `0.' When the CY7C66113 is used the P3[7] should be written with a `0.' In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high impedance input state (`1' in open drain mode). Writing a `0' to a GPIO pin drives the pin LOW. In this state, a `0' is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
9.1
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins.
GPIO Configuration Bit # 7 Bit Name Read/Write Reset Port 3 Config Bit 1 R/W 0 6 Port 3 Config Bit 0 R/W 0 5 Port 2 Config Bit 1 R/W 0 4 Port 2 Config Bit 0 R/W 0 3 Port 1 Config Bit 1 R/W 0 2 Port 1 Config Bit 0 R/W 0 1 Port 0 Config Bit 1 R/W 0 ADDRESS 0x08 0 Port 0 Config Bit 0 R/W 0
Figure 9-6. GPIO Configuration Register
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As shown in Table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (LOW to HIGH), and a negative polarity on an input pin represents a falling edge interrupt (HIGH to LOW). The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 16-1) is enabled, the Interrupt Enable Sense (bit 2, Figure 15-1) is set, and the GPIO pin of the port sees an event matching the interrupt polarity. The driving state of each GPIO pin is determined by the value written to the pin's Data Register (Figure 9-2 through Figure 9-5) and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-6). These ports are configured on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed in Table 9-1. As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. During reset, all of the bits in the GPIO Configuration Register are written with `0' to select Hi-Z mode for all GPIO ports as the default configuration. Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 Output LOW Resistive Output LOW Output HIGH Output LOW Hi-Z Output LOW Hi-Z 0 1 0 1 0 1 0 1 Interrupt Polarity Disabled - (Falling Edge) Disabled Disabled Disabled - (Falling Edge) Disabled + (Rising Edge)
Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO drive strength are: * Output LOW Mode: The pin's Data Register is set to `0' Writing `0' to the pin's Data Register puts the pin in output LOW mode, regardless of the contents of the Port Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3. * Output HIGH Mode: The pin's Data Register is set to 1 and the Port Configuration Bits[1:0] is set to `10' In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing ... of current. * Resistive Mode: The pin's Data Register is set to 1 and the Port Configuration Bits[1:0] is set to `11' Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14k resistor. In resistive mode, the pin may serve as an input. Reading the pin's Data Register returns a logic HIGH if the pin is not driven LOW by an external source. * Hi-Z Mode: The pin's Data Register is set to1 and Port Configuration Bits[1:0] is set either `00' or `01' Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the Port Data Register returns the actual logic value on the port pins.
9.2
GPIO Interrupt Enable Ports
Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0-3 Interrupt Enable registers provide this feature with an interrupt enable bit for each GPIO pin. When HAPI mode (Section 14.0) is enabled the GPIO interrupts are blocked, including ports not used by HAPI, so GPIO pins cannot be used as interrupt sources. During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a `1' to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in Section 16.8.
Port 0 Interrupt Enable Bit # 7 Bit Name Read/Write Reset P0.7 Intr Enable W 0 6 P0.6 Intr Enable W 0 5 P0.5 Intr Enable W 0 4 P0.4 Intr Enable W 0 3 P0.3 Intr Enable W 0 2 P0.2 Intr Enable W 0 1 P0.1 Intr Enable W 0 ADDRESS 0x04 0 P0.0 Intr Enable W 0
Figure 9-7. Port 0 Interrupt Enable
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Port 1 Interrupt Enable Bit # Bit Name Read/Write Reset 7 P1.7 Intr Enable W 0 6 P1.6 Intr Enable W 0 5 P1.5 Intr Enable W 0 4 P1.4 Intr Enable W 0 3 Reserved W 0 2 P0.2 Intr Enable W 0 1 P1.1 Intr Enable W 0 ADDRESS 0x05 0 P1.0 Intr Enable W 0
Figure 9-8. Port 1 Interrupt Enable
Port 2 Interrupt Enable Bit # 7 Bit Name Read/Write Reset P0.7 Intr Enable W 0 6 P0.6 Intr Enable W 0 5 P0.5 Intr Enable W 0 4 P0.4 Intr Enable W 0 3 P0.3 Intr Enable W 0 2 Reserved W 0 1 Reserved W 0 ADDRESS 0x06 0 Reserved W 0
Figure 9-9. Port 2 Interrupt Enable
Port 3 Interrupt Enable Bit # 7 Bit Name Read/Write Reset Reserved W 0 6 Reserved W 0 5 Reserved W 0 4 Reserved W 0 3 Reserved W 0 2 Reserved W 0 1 P3.1 Intr Enable W 0 ADDRESS 0x07 0 P0.3 Intr Enable W 0
Figure 9-10. Port 3 Interrupt Enable
10.0
DAC Port
The CY7C66113 features a programmable sink current 8 bit port which is also known as DAC port. Each of these port I/O pins have a programmable current sink. Writing a `1' to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14-k resistor. When a `0' is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. This causes the Isink DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of the DAC port pin. VCC
Internal Data Bus Data Out Latch Q1 Suspend (Bit 3 of Register 0xFF) 14 k DAC Write Isink Register Internal Buffer 4 bits Isink DAC
DAC I/O Pin
DAC Read Interrupt Enable Interrupt Polarity Interrupt Logic
to Interrupt Controller
Figure 10-1. Block Diagram of a DAC Pin The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register (Figure 10-3) for that output pin. DAC[1:0] are high current outputs that are programmable from 3.2 mA to 16 mA (typical). DAC[7:2] are low current outputs, programmable from 0.2 mA to 1.0 mA (typical). When the suspend bit in Processor Status and Control Register (Figure 15-1) is set, the Isink DAC block of the DAC circuitry is disabled. Special care should be taken when the CY7C66113 device is placed in the suspend. The DAC Port Data Register(Figure 10-2) should normally be loaded with all `1's (Figure 15-1) before setting the suspend bit. If any of the DAC bits
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are set to `0' when the device is suspended, that DAC input will float. The floating pin could result in excessive current consumption by the device, unless an external load places the pin in a deterministic state.
DAC Port Data Bit # Bit Name Read/Write Reset 7 DAC[7] R/W 1 6 DAC[6] R/W 1 5 DAC[5] R/W 1 4 DAC[4] R/W 1 3 DAC[3] R/W 1 2 DAC[2] R/W 1 1 DAC[1] R/W 1 ADDRESS 0x30 0 DAC[0] R/W 1
Figure 10-2. DAC Port Data Bit [1..0]: High Current Output 3.2 mA to 16 mA typical 1= I/O pin is an output pulled HGH through the 14-k resistor. 0 = I/O pin is an input with an internal 14-k pull-up resistor. Bit [7..2]: Low Current Output 0.2 mA to 1 mA typical 1= I/O pin is an output pulled HGH through the 14-k resistor. 0 = I/O pin is an input with an internal 14-k pull-up resistor.
10.1
DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F, controls the current to DAC[7].
DAC Sink Register Bit # 7 Bit Name Read/Write Reset Reserved 6 Reserved 5 Reserved 4 Reserved 3 Isink[3] W 0 2 Isink[2] W 0 1 Isink[1] W 0 ADDRESS 0x38 -0x3F 0 Isink[0] W 0
Figure 10-3. DAC Sink Register Bit [4..0]: Isink [x] (x= 0..4) Writing all `0's to the Isink register causes 1/5 of the max current to flow through the DAC I/O pin. Writing all `1's to the Isink register provides the maximum current flow through the pin. The other 14 states of the DAC sink current are evenly spaced between these two values. Bit [7..5]: Reserved
10.2
DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature with an interrupt enable bit for each DAC I/O pin. All of the DAC Port Interrupt Enable register bits are cleared to `0' during a reset. All DAC pins share a common interrupt, as explained in Section 16.7.
DAC Port Interrupt Bit # 7 Bit Name Read/Write Reset Enable Bit 7 W 0 6 Enable Bit 6 W 0 5 Enable Bit 5 W 0 4 Enable Bit 4 W 0 3 Enable Bit 3 W 0 2 Enable Bit 2 W 0 1 Enable Bit 1 W 0 ADDRESS 0x31 0 Enable Bit 0 W 0
Figure 10-4. DAC Port Interrupt Enable Bit [7..0]: Enable bit x (x= 0..7) 1= Enables interrupts from the corresponding bit position; 0= Disables interrupts from the corresponding bit position As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register. Writing a `0' to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. Writing a `1' to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are cleared during a reset.
DAC Port Interrupt Bit # 7 Bit Name Read/Write Enable Bit 7 W 6 Enable Bit 6 W 5 Enable Bit 5 W 4 Enable Bit 4 W 3 Enable Bit 3 W 2 Enable Bit 2 W 1 Enable Bit 1 W ADDRESS 0x32 0 Enable Bit 0 W
Figure 10-5. DAC Port Interrupt Polarity Document #: 38-08024 Rev. *A Page 23 of 58
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Reset 0 0 0 0 0 0 0 0
Figure 10-5. DAC Port Interrupt Polarity Bit [7..0]: Enable bit x (x= 0..7) 1= Selects positive polarity (rising edge) that causes an interrupt (if enabled); 0= Selects negative polarity (falling edge) that causes an interrupt (if enabled).
11.0
12-bit Free-running Timer
The 12-bit timer operates with a 1-s tick, provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.
Timer LSB Bit # Bit Name Read/Write Reset 7 Timer Bit 7 R 0 6 Timer Bit 6 R 0 5 Timer Bit 5 R 0 4 Timer Bit 4 R 0 3 Timer Bit 3 R 0 2 Timer Bit 2 R 0 1 Timer Bit 1 R 0 ADDRESS 0x24 0 Timer Bit 0 R 0
Figure 11-1. Timer LSB Register Bit [7:0]: Timer lower eight bits
Timer MSB Bit # Bit Name Read/Write Reset 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Timer Bit 11 R 0 2 Timer Bit 10 R 0 1 Timer Bit 9 R 0 ADDRESS 0x25 0 Timer Bit 8 R 0
Figure 11-2. Timer MSB Register Bit [3:0]: Timer higher nibble Bit [7:4]: Reserved
1.024-ms interrupt 128-s interrupt
11 10 9
8
7
6
5
4
3
2
1
0
1 MHz clock
L
L2 L1 L0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
8 To Timer Registers
Figure 11-3. Timer Block Diagram
12.0
I2C and HAPI Configuration Register
Internal hardware supports communication with external devices through two interfaces: a two-wire I2C-compatible, and a HAPI for 1, 2, or 3 byte transfers. The I2C-compatible and HAPI functions, discussed in detail in Sections 13.0 and 14.0, share a common configuration register (see Figure 12-1)[3]. All bits of this register are cleared on reset. I2C Configuration
Bit # Bit Name Read/Write 7 I2C Position R/W 6 Reserved 5 LEMPTY Polarity R/W 4 DRDY Polarity R/W 3 Latch Empty R 2 Data Ready R 1 HAPI Port Width Bit 1 R/W ADDRESS 0x09 0 HAPI Port Width Bit 0 R/W
Figure 12-1. Document #: 38-08024 Rev. *A
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Reset Note: 3. 0 0 0 0 0 0 0 0
Figure 12-1.
HAPI/I2
C Configuration Register
Bits [7,1:0] of the HAPI/I C Configuration Register control the pin out configuration of the HAPI and I2C-compatible interfaces. Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and Table 12-2 shows I2C pin location configuration options. These I2C-compatible options exist due to pin limitations in certain packages, and to allow simultaneous HAPI and I2C-compatible operation. HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described in Section 14.0. The I2C-compatible interface must be separately enabled as described in Section13.0. Table 12-1. HAPI Port Configuration Port Width (Bit 0 and 1, Figure 12-1)
11 10 01 00
I2C-compatible function must be separately enabled, as described in Section 13.0. 2
HAPI Port Width
24 Bits: P3[7:0], P1[7:0], P0[7:0] 16 Bits: P1[7:0], P0[7:0] 8 Bits: P0[7:0] No HAPI Interface
Table 12-2. I2C Port Configuration I2C Position (Bit 7, Figure 12-1)
Don't Care 0 1 1 0 0
I2C Port Width (Bit 1, Figure 12-1)
I2C Position I2C on P2[1:0], 0:SCL, 1:SDA I2C on P1[1:0], 0:SCL, 1:SDA I2C on P2[1:0], 0:SCL, 1:SDA
13.0
I2C-compatible Controller
The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the hardware keeps the I2C-compatible bus idle if necessary. The I2C-compatible interface generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in Section 16.9. The I2C-compatible interface consists of two registers, an I2C Data Register (Figure 13-1) and an I2C Status and Control Register (Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I2C Status and Control Register should only be monitored after the I2C interrupt, as all bits are valid at that time. Polling this register at other times could read misleading bit status if a transaction is underway. The I2C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of GPIO port 1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I2C Configuration Register, which is used to set the locations of the configurable I2C pins. Once the I2C-compatible functionality is enabled by setting bit 0 of the I2C Status & Control Register, the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the GPIO Configuration Register. The electrical characteristics of the I2C-compatible interface is the same as that of GPIO ports 1 and 2. Note that the IOL (max) is 2 mA @ VOL = 2.0V for ports 1 and 2. All control of the I2C clock and data lines is performed by the I2C-compatible block.
I2C Data Bit # Bit Name Read/Write Reset 7 I2C Data 7 R/W X 6 I2C Data 6 R/W X 5 I2C Data 5 R/W X 4 I2C Data 4 R/W X 3 I2C Data 3 R/W X 2 I2C Data 2 R/W X 1 I2C Data 1 R/W X ADDRESS 0x29 0 I2C Data 0 R/W X
Figure 13-1. Bits [7..0] : I2C Data Contains 8-bit data on the I2C Bus.
I2C Status and Control Bit # 7 6 5 4
I2C
Data Register
3
2
1
ADDRESS 0x28 0
Figure 13-2. I2C Status and Control Register
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Bit Name Read/Write Reset MSTR Mode R/W 0 Continue/Busy Xmit Mode R/W 0 R/W 0 ACK R/W 0 Addr R/W 0 ARB Lost/Restart R/W 0 Received Stop R/W 0 I2C Enable R/W 0
Figure 13-2. I C Status and Control Register The I2C Status and Control register bits are defined in Table 14-1, with a more detailed description following. Table 13-1. I2C Status and Control Register Bit Definitions Bit
0 1 2 3 4 5 6 7
2
Name I2C Enable Received Stop
Description When set to `1', the I2C-compatible function is enabled. When cleared, I2C GPIO pins operate normally. Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not ACK the last transaction).
ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise. Write to 1 in master mode to perform a restart sequence (also set Continue bit). Addr ACK Xmit Mode Continue/Busy MSTR Mode Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. Reads 0 otherwise. This bit should always be written as 0. In receive mode, write 1 to generate ACK, 0 for no ACK. In transmit mode, reads 1 if ACK was received, 0 if no ACK received. Write to 1 for transmit mode, 0 for receive mode. Write 1 to indicate ready for next transaction. Reads 1 when I2C-compatible block is busy with a transaction, 0 when transaction is complete. Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration. Clearing from 1 to 0 generates Stop bit.
Bit 7 : MSTR Mode Setting this bit to 1 causes the I2C-compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes are initiated by setting the Continue bit, as described below. Clearing this bit (set to 0) causes the GPIO pins to operate normally In master mode, the I2C-compatible block generates the clock (SCK), and drives the data line as required depending on transmit or receive state. The I2C-compatible block performs any required arbitration and clock synchronization. IN the event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the external master is completed. When MSTR Mode is cleared from 1 to 0 by a firmware write, an I2C Stop bit is generated. Bit 6 : Continue/Busy This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words, the bit has responded to an interrupt request and has completed the required update or read of the data register. During a read this bit indicates if the hardware is busy and is locking out additional writes to the I2C Status and Control register. This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C interrupt, the I2C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the firmware to make one control register write without the need to check the Busy bit. Bit 5 : Xmit Mode This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit sets the part in receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I2C address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases always cause transmit mode for the first byte. Bit 4 : ACK This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal on the I2C-compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C-compatible bus at the ACK bit time. During transmits (Xmit Mode = 1), this bit should be cleared. Bit 3 : Addr
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This bit is set by the I2C-compatible block during the first byte of a slave receive transaction, after an I2C start or restart. The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. Bit 2 : ARB Lost/Restart This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. Bit 1 : Receive Stop This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the firmware terminates the I2C transaction by not acknowledging the previous byte transmitted on the I2C-compatible bus, e.g. in receive mode if firmware sets the Continue bit and clears the ACK bit. Bit 0 : I2C Enable Set this bit to override GPIO definition with I2C-compatible function on the two I2C-compatible pins. When this bit is cleared, these pins are free to function as GPIOs. In I2C-compatible mode, the two pins operate in open drain mode, independent of the GPIO configuration setting.
14.0
Hardware Assisted Parallel Interface (HAPI)
The CY7C66x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I2C Configuration Register (Figure 12-1), bits 1 and 0. Signals are provided on Port 2 to control the HAPI interface. Table 14-1 describes these signals and the HAPI control bits in the HAPI/I2C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (Figure 9-6) to be overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3 OFF in Figure 9-1). Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions Pin
P2[2] P2[3] P2[4] P2[5] P2[6] Bit 2 3 4
Name
LatEmptyPin DReadyPin STB OE CS Name Data Ready Latch Empty DRDY Polarity
Direction
Out Out In In In R/W R R R/W
Description (Port 2 Pin) Ready for more input data from external interface. Output data ready for external interface. Strobe signal for latching incoming data. Output Enable, causes chip to output data. Chip Select (Gates STB and OE). Description (HAPI/I2C Configuration Register) Asserted after firmware writes data to Port 0, until OE driven LOW. Asserted after firmware reads data from Port 0, until STB driven LOW. Determines polarity of Data Ready bit and DReadyPin: If 0, Data Ready is active LOW, DReadyPin is active HIGH. If 1, Data Ready is active HIGH, DReadyPin is active LOW. Determines polarity of Latch Empty bit and LatEmptyPin: If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH. If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
5
LEMPTY Polarity
R/W
HAPI Read by External Device from CY7C66x13: In this case (see Figure 25-3), firmware writes data to the GPIO ports. If 16-bit or 24-bit transfers are being made, Port 0 should be written last, since writes to Port 0 asserts the Data Ready bit and the DReadyPin to signal the external device that data is available. The external device then drives the OE and CS pins active (LOW), which causes the HAPI data to be output on the port pins. When OE is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. At that point, firmware can reload the HAPI latches for the next output, again writing Port 0 last. The Data Ready bit reads the opposite state from the external DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin is active HIGH, and the Data Ready bit is active LOW. HAPI Write by External Device to CY7C66x13:
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In this case (see Figure 25-4), the external device drives the STB and CS pins active (LOW) when it drives new data onto the port pins. When this happens, the internal latches become full, which causes the Latch Empty bit to be deasserted. When STB is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. Firmware then reads the parallel ports to empty the HAPI latches. If 16-bit or 24-bit transfers are being made, Port 0 should be read last because reads from Port 0 assert the Latch Empty bit and the LatEmptyPin to signal the external device for more data. The Latch Empty bit reads the opposite state from the external LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0, LatEmptyPin is active HIGH, and the Latch Empty bit is active LOW.
15.0
Processor Status and Control Register
6 Watchdog Reset R/W 0 5 USB Bus Reset Interrupt R/W 0 4 Power-On Reset R/W 1 3 Suspend R/W 0 2 Interrupt Enable Sense R 0 1 Reserved R/W 0 ADDRESS 0xFF 0 Run R/W 1
Processor Status and Control Bit # 7 Bit Name Read/Write Reset IRQ Pending R 0
Figure 15-1. Processor Status and Control Register Bit 0: Run This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor remains halted until an appropriate reset occurs (power-on or Watchdog). This bit should normally be written as a `1.' Bit 1: Reserved Bit 1 is reserved and must be written as a zero. Bit 2: Interrupt Enable Sense This bit indicates whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. A `0' indicates that interrupts are masked off and a `1' indicates that the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (Figure 16-1) and USB End Point Interrupt Enable Register (Figure 16-2). Instructions DI, EI, and RETI manipulate the state of this bit. Bit 3: Suspend Writing a `1' to the Suspend bit halts the processor and cause the microcontroller to enter the suspend mode that significantly reduces power consumption. A pending, enabled interrupt or USB bus activity causes the device to come out of suspend. After coming out of suspend, the device resumes firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR attempting to put the part into suspend is ignored if USB bus activity is present. See Section 8.0 for more details on suspend mode operation. Bit 4: Power-on Reset The Power-on Reset is set to `1' during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on condition or a Watchdog timeout. A POR event may be followed by a WDR before firmware begins executing, as explained below. Bit 5: USB Bus Reset Interrupt The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detected on receiving a USB Bus Reset signal on the upstream port. The USB Bus Reset signal is a single-ended zero (SE0) that lasts from 12 to 16 s. An SE0 is defined as the condition in which both the D+ line and the D- line are LOW at the same time. Bit 6: WDR The WDR is set during a reset initiated by the WDT. This indicates the WDT went for more than tWATCH (8 ms minimum) between Watchdog clears. This can occur with a POR event, as noted below. Bit 7: IRQ Pending The IRQ pending, when set, indicates that one or more of the interrupts has been recognized as active. An interrupt remains pending until its interrupt enable bit is set (Figure 16-1, Figure 16-2) and interrupts are globally enabled. At that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. During power-up, the Processor Status and Control Register is set to 00010001, which indicates a POR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). During the 96 ms suspend at start-up (explained in Section 7.1), a WDR also occurs unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend interval, firmware reads 01010001 from the Status and Control Register after power-up. Normally, the POR bit should be cleared so a subsequent WDR can be clearly identified. If an upstream bus reset is received before firmware examines this register, the Bus Reset bit may also be set.
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During a WDR, the Processor Status and Control Register is set to 01XX0001, which indicates a WDR (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The WDR does not effect the state of the POR and the Bus Reset Interrupt bits.
16.0
Interrupts
Interrupts are generated by the GPIO/DAC pins, the internal timers, I2C-compatible or HAPI operation, the internal USB hub, or on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a `1' to a bit position enables the interrupt associated with that bit position.
Global Interrupt Enable Register Bit # Bit Name 7 Reserved 6 C Interrupt Enable R/W 0 I2 5 GPIO Interrupt Enable R/W 0 4 Reserved 3 USB Hub Interrupt Enable R/W 0 2 1.024-ms Interrupt Enable R/W 0 1 128-s Interrupt Enable R/W 0 ADDRESS 0X20 0 USB Bus RST Interrupt Enable R/W 0
Read/Write Reset
-
X
Figure 16-1. Global Interrupt Enable Register Bit 0 : USB Bus RST Interrupt Enable 1= Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (refer to section 14.3). Bit 1 :128-s Interrupt Enable 1 = Enable Timer interrupt every 128 s; 0 = Disable Timer Interrupt for every 128 s. Bit 2 : 1.024-ms Interrupt Enable 1= Enable Timer interrupt every 1.024 ms ; 0 = Disable Timer Interrupt every 1.024 ms. Bit 3 : USB Hub Interrupt Enable 1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.) Bit 4 : Reserved Bit 5 : GPIO Interrupt Enable 1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO. (Refer to subsections 14.7, 9.1, and 9.2.) Bit 6 : I2C Interrupt Enable 1= Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.) Bit 7 : Reserved.
USB Endpoint Interrupt Enable Bit # Bit Name Read/Write Reset 7 Reserved 6 Reserved 5 Reserved 4 EPB1 Interrupt Enable R/W 0 3 EPB0 Interrupt Enable R/W 0 2 EPA2 Interrupt Enable R/W 0 1 EPA1 Interrupt Enable R/W 0 ADDRESS 0X21 0 EPA0 Interrupt Enable R/W 0
Figure 16-2. USB Endpoint Interrupt Enable Register
Bit 0: EPA0 Interrupt Enable
1= Enable Interrupt on data activity through endpoint A0; 0= Disable Interrupt on data activity through endpoint A0. Bit 1: EPA1 Interrupt Enable 1= Enable Interrupt on data activity through endpoint A1; 0= Disable Interrupt on data activity through endpoint A1. Bit 2: EPA2 Interrupt Enable 1= Enable Interrupt on data activity through endpoint A2; 0= Disable Interrupt on data activity through endpoint A2. Bit 3: EPB0 Interrupt Enable 1= Enable Interrupt on data activity through endpoint B0; 0= Disable Interrupt on data activity through endpoint B0. Bit 4: EPB1 Interrupt Enable 1= Enable Interrupt on data activity through endpoint B1; 0= Disable Interrupt on data activity through endpoint B1. Bit [7..5] : Reserved Document #: 38-08024 Rev. *A Page 29 of 58
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During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively, disabling all interrupts. The interrupt controller contains a separate flip-flop for each interrupt. See Figure 16-3 for the logic block diagram of the interrupt controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction. When servicing an interrupt, the hardware does the following: 1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the Processor Status and Control Register, Figure 15-1). 2. Clears the flip-flop of the current interrupt. 3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector, see Section 16.1). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited only by the available stack space. The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed. The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 16-1. The lowest-numbered interrupt (USB Bus Reset interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority.
USB Reset Clear Interrupt Vector USB Reset IRQ 128-s CLR 128-s IRQ 1-ms CLR 1-ms IRQ IRQout AddrA EP0 CLR AddrA EP0 IRQ AddrA EP1 CLR AddrA EP1 IRQ AddrA EP2 CLR AddrA EP2 IRQ AddrB EP0 CLR AddrB EP0 IRQ AddrB EP1 CLR AddrB EP1 IRQ Hub CLR Hub IRQ DAC CLR DAC IRQ GPIO CLR GPIO IRQ I2C CLR CLR 1 I2C Int D CLK Q Enable [6] (Reg 0x20) I2C IRQ Interrupt Priority Encoder To CPU
CLR 1 USB Reset Int D CLK Q Enable [0] (Reg 0x20)
CPU
IRQ Sense IRQ
CLR 1 AddrA ENP2 Int D CLK Q Enable [2] (Reg 0x21)
Global Interrupt Enable Bit CLR
Int Enable Sense
Controlled by DI, EI, and RETI Instructions
Interrupt Acknowledge
Figure 16-3. Interrupt Controller Function Diagram
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Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h--which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes. Table 16-1. Interrupt Vector Assignments Interrupt Vector Number Not Applicable 1 2 3 4 5 6 7 8 9 10 11 12 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 ROM Address Function Execution after Reset begins here USB Bus Reset interrupt 128-s timer interrupt 1.024-ms timer interrupt USB Address A Endpoint 0 interrupt USB Address A Endpoint 1 interrupt USB Address A Endpoint 2 interrupt USB Address B Endpoint 0 interrupt USB Address B Endpoint 1 interrupt USB Hub interrupt DAC interrupt GPIO interrupt I2C interrupt
16.2
Interrupt Latency
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction).
Interrupt latency can be calculated from the following equation: Interrupt latency =
For example, if a five-clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20/12 MHz = 1.667 s.
16.3
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for 12-16 s. SE0 is defined as the condition in which both the D+ line and the D- line are LOW. A USB Bus Reset may be recognized for an SE0 as short as 12 s, but is always recognized for an SE0 longer than 16 s. When a USB Bus Reset is detected, bit 5 of the Processor Status and Control Register (Figure 15-1) is set to record this event. In addition, the controller clears the following registers: SIE Section: Hub Section: USB Device Address Registers (0x10, 0x40) Hub Ports Connect Status (0x48) Hub Ports Enable (0x49) Hub Ports Speed (0x4A) Hub Ports Suspend (0x4D) Hub Ports Resume Status (0x4E) Hub Ports SE0 Status (0x4F) Hub Ports Data (0x50) Hub Downstream Force (0x51). A USB Bus Reset Interrupt is generated at the end of the USB Bus Reset condition when the SE0 state is deasserted. If the USB reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1.
16.4
Timer Interrupt
There are two periodic timer interrupts: the 128-s interrupt and the 1.024-ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first.
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16.5 USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of the transaction (e.g. on the host's ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an IN transaction, no interrupt is generated.
16.6
USB Hub Interrupt
A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port Enable Register (Figure 18-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive the port (i.e., the port is being forced).
16.7
DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled. The interrupt polarity for each DAC I/O pin is programmable. A positive polarity is a rising edge input while a negative polarity is a falling edge input. All of the DAC pins share a single interrupt vector, which means the firmware needs to read the DAC port to determine which pin or pins caused an interrupt. If one DAC pin has triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process.
16.8
GPIO/HAPI Interrupt
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt logic is shown in Figure 16-4. Refer to Sections 9.1 and 9.2 for more information about setting GPIO interrupt polarity and enabling individual GPIO interrupts.
Port Configuration Register
OR Gate (1 input per GPIO pin)
GPIO Interrupt Flip Flop 1 D Q Interrupt Priority Encoder IRQout Interrupt Vector
GPIO Pin
M U X
CLR
1 = Enable 0 = Disable IRA
Port Interrupt Enable Register
1 = Enable 0 = Disable
Global GPIO Interrupt Enable (Bit 5, Register 0x20)
Figure 16-4. GPIO Interrupt Structure If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. When HAPI is enabled, the HAPI logic takes over the interrupt vector and blocks any interrupt from the GPIO bits, including ports/bits not being used by HAPI. Operation of the HAPI interrupt is independent of the GPIO specific bit interrupt enables, and is enabled or disabled only by bit 5 of the Global Interrupt Enable Register (0x20) when HAPI is enabled. The settings of the GPIO bit interrupt enables on ports/bits not used by HAPI still effect the CMOS mode operation of those ports/bits. The effect of modifying the interrupt bits while the Port Config bits are set to "10" is shown in Table 9-1. The events that generate HAPI interrupts are described in Section 14.0.
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16.9 I2C Interrupt
The after various events on the I2C-compatible bus to signal the need for firmware interaction. This generally involves reading the I C Status and Control Register (Figure 13-2) to determine the cause of the interrupt, loading/reading the I2C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 15-1) to initiate the subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I2C registers. Refer to Section 13.0 for details on the I2C registers. When enabled, the I2C-compatible state machines generate interrupts on completion of the following conditions. The referenced bits are in the I2C Status and Control Register. 1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit MODE, and Continue/Busy bits appropriately for the next byte. 2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction where the ACK bit was cleared to 0, no stop bit detection occurs. 3. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit MODE and Continue/Busy bits as required. 4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and set the Xmit MODE, MSTR MODE, and Continue/Busy bits appropriately. Clearing the MSTR MODE bit issues a stop signal to the I2C-compatible bus and return to the idle state. 5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state machine to issue a stop signal to the I2C-compatible bus and leave the I2C-compatible hardware in the idle state. 6. When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately and then waits for a stop signal on the I2C-compatible bus to generate the interrupt. The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written, firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit, without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I2C register contents may be changed by the hardware during the transaction, until the I2C interrupt occurs. I2C interrupt occurs 2
17.0
USB Overview
The USB hardware includes a USB Hub repeater with one upstream and four downstream ports. The USB Hub repeater interfaces to the microcontroller through a full-speed Serial Interface Engine. An external series resistor of Rext must be placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification. The CY7C66x13 microcontroller can provide the functionality of a compound device consisting of a USB hub and permanently attached functions.
17.1
USB Serial Interface Engine
The SIE allows the CY7C66x13 microcontroller to communicate with the USB host through the USB repeater portion of the hub. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: * Bit stuffing/unstuffing * Checksum generation/checking * ACK/NAK/STALL * Token type identification * Address checking. Firmware is required to handle the following USB interface tasks: * Coordinate enumeration by responding to SETUP packets * Fill and empty the FIFOs * Suspend/Resume coordination * Verify and select DATA toggle values.
17.2
USB Enumeration
The internal hub and any compound device function are enumerated under firmware control. The hub is enumerated first, followed by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration process of the CY7C66x13 by the USB host. For a detailed description of the enumeration process, refer to the USB specification. Document #: 38-08024 Rev. *A Page 33 of 58
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In this description, "Firmware" refers to embedded firmware in the CY7C66x13 controller. 1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor. 2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables. 3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus, via the on-chip FIFOs. 4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device. 5. Firmware stores the new address in its USB Device Address Register (for example, as Address B) after the no-data control sequence completes. 6. The host sends a request for the Device descriptor using the new USB address. 7. Firmware decodes the request and retrieves the Device descriptor from program memory tables. 8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus. 9. The host generates control reads from the device to request the Configuration and Report descriptors. 10.Once the device receives a Set Configuration request, its functions may now be used. 11.Following enumeration as a hub, Firmware can optionally indicate to the host that a compound device exists (for example, the keyboard in a keyboard/hub device). 12.The host carries out the enumeration process with this additional function as though it were attached downstream from the hub. 13.When the host assigns an address to this device, it is stored as the other USB address (for example, Address A).
18.0
USB Hub
A USB hub is required to support: * Connectivity behavior: service connect/disconnect detection * Bus fault detection and recovery * Full-/low-speed device support. These features are mapped onto a hub repeater and a hub controller. The hub controller is supported by the processor integrated into the CY7C66013 and CY7C66113 microcontrollers. The hardware in the hub repeater detects whether a USB device is connected to a downstream port and the interface speed of the downstream device. The connection to a downstream port is through a differential signal pair (D+ and D-). Each downstream port provided by the hub requires external RUDN resistors from each signal line to ground, so that when a downstream port has no device connected, the hub reads a LOW (zero) on both D+ and D-. This condition is used to identify the "no connect" state. The hub must have a resistor RUUP connected between its upstream D+ line and VREG to indicate it is a full speed USB device. The hub generates an EOP at EOF1, in accordance with the USB 1.1 Specification, Section 11.2.2.
18.1
Connecting/Disconnecting a USB Device
A low-speed (1.5 Mbps) USB device has a pull-up resistor on the D- pin. At connect time, the bias resistors set the signal levels on the D+ and D- lines. When a low-speed device is connected to a hub port, the hub sees a LOW on D+ and a HIGH on D-. This causes the hub repeater to set a connect bit in the Hub Ports Connect Status register for the downstream port. Then the hub repeater generates a Hub Interrupt to notify the microcontroller that there has been a change in the Hub downstream status. A full-speed (12 Mbps) USB device has a pull-up resistor from the D+ pin, so the hub sees a HIGH on D+ and a LOW on D-. In this case, the hub repeater sets a connect bit in the Hub Ports Connect Status register, clears a bit in the Hub Ports Speed register (for full-speed), and generates a Hub Interrupt to notify the microcontroller of the change in Hub status. The firmware sets the speed of this port in the Hub Ports Speed Register (see Figure 18-2) Connects are recorded by the time a non-SE0 state lasts for more than 2.5 s on a downstream port. When a USB device is disconnected from the Hub, the downstream signal pair eventually floats to a single-ended zero state. The hub repeater recognizes a disconnect once the SE0 state on a downstream port lasts from 2.0 to 2.5 s. On a disconnect, the corresponding bit in the Hub Ports Connect Status register is cleared, and the Hub Interrupt is generated.
Hub Ports Connect Status Bit # 7 Bit Name Read/Write Reset Reserved R/W 0 6 Port 7 Connect Status R/W 0 5 Port 6 Connect Status R/W 0 4 Port 5 Connect Status R/W 0 3 Port 4 Connect Status R/W 0 2 Port 3 Connect Status R/W 0 1 Port 2 Connect Status R/W 0 ADDRESS 0 0x48
Port 1 Connect Status R/W 0
Figure 18-1. Hub Ports Connect Status
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Bit [0..6] : Port x Connect Status (where x = 1..7) When set to 1, Port x is connected; When set to 0, Port x is disconnected. Bit 7 : Reserved. Set to 0. The Hub Ports Connect Status register is cleared to zero by reset or USB bus reset, then set to match the hardware configuration by the hub repeater hardware. The Reserved bit [7] should always read as `0' to indicate no connection.
Hub Ports Speed Bit # Bit Name Read/Write Reset 7 Reserved R/W 0 6 Port 7 Speed R/W 0 5 Port 6 Speed R/W 0 4 Port 5 Speed R/W 0 3 Port 4 Speed R/W 0 2 Port 3 Speed R/W 0 1 Port 2 Speed R/W 0 ADDRESS 0 Port 1 Speed R/W 0 0x4A
Figure 18-2. Hub Ports Speed
Bit [0..6] : Port x Speed (where x = 1..7) Set to 1 if the device plugged in to Port x is Low Speed; Set to 0 if the device plugged in to Port x is Full Speed. Bit 7 : Reserved. Set to 0. The Hub Ports Speed register is cleared to zero by reset or bus reset. This must be set by the firmware on issuing a port reset. The Reserved bit [7] should always read as `0.'
18.2
Enabling/Disabling a USB Device
After a USB device connection has been detected, firmware must update status change bits in the hub status change data structure that is polled periodically by the USB host. The host responds by sending a packet that instructs the hub to reset and enable the downstream port. Firmware then sets the bit in the Hub Ports Enable register, Figure 18-3, for the downstream port. The hub repeater hardware responds to an enable bit in the Hub Ports Enable register by enabling the downstream port, so that USB traffic can flow to and from that port. If a port is marked enabled and is not suspended, it receives all USB traffic from the upstream port, and USB traffic from the downstream port is passed to the upstream port (unless babble is detected). Low-speed ports do not receive full-speed traffic from the upstream port. When firmware writes to the Hub Ports Enable register to enable a port, the port is not enabled until the end of any packet currently being transmitted. If there is no USB traffic, the port is enabled immediately. When a USB device disconnection has been detected, firmware must update status bits in the hub change status data structure that is polled periodically by the USB host. In suspend, a connect or disconnect event generates an interrupt (if the hub interrupt is enabled) even if the port is disabled.
Hub Ports Enable Register Bit # 7 Bit Name Read/Write Reset Reserved R/W 0 6 Port 7 Enable R/W 0 5 Port 6 Enable R/W 0 4 Port 5 Enable R/W 0 3 Port 4 Enable R/W 0 2 Port 3 Enable R/W 0 1 Port 2 Enable R/W 0 ADDRESS 0 0x49
Port 1 Enable R/W 0
Figure 18-3. Hub Ports Enable Register
Bit [0..6] : Port x Enable (where x = 1..7) Set to 1 if Port x is enabled; Set to 0 if Port x is disabled. Bit 7 : Reserved. Set to 0. The Hub Ports Enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition. A port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. Babble is defined as: * Any non-idle downstream traffic on an enabled downstream port at EOF2 * Any downstream port with upstream connectivity established at EOF2 (i.e., no EOP received by EOF2).
18.3
Hub Downstream Ports Status and Control
Data transfer on hub downstream ports is controlled according to the bit settings of the Hub Downstream Ports Control Register (Figure 18-4). Each downstream port is controlled by two bits, as defined in Table 18-1 below. The Hub Downstream Ports Control Document #: 38-08024 Rev. *A Page 35 of 58
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Register is cleared upon reset or bus reset, and the reset state is the state for normal USB traffic. Any downstream port being forced must be marked as disabled (Figure 18-3) for proper operation of the hub repeater. Firmware should use this register for driving bus reset and resume signaling to downstream ports. Controlling the port pins through this register uses standard USB edge rate control according to the speed of the port, set in the Hub Port Speed Register. The downstream USB ports are designed for connection of USB devices, but can also serve as output ports under firmware control. This allows unused USB ports to be used for functions such as driving LEDs or providing additional input signals. Pulling up these pins to voltages above VREF may cause current flow into the pin. This register is not reset by bus reset. These bits must be cleared before going into suspend.
Hub Downstream Ports Control Register Bit # Bit Name Read/Write Reset 7 Port 4 Control Bit 1 R/W 0 6 Port 4 Control Bit 0 R/W 0 5 Port 3 Control Bit 1 R/W 0 4 Port 3 Control Bit 0 R/W 0 3 Port 2 Control Bit 1 R/W 0 2 Port 2 Control Bit 0 R/W 0 1 Port 1 Control Bit 1 R/W 0 ADDRESS 0 Port 1 Control Bit 0 R/W 0 0x4B
Figure 18-4. Hub Downstream Ports Control Register
Table 18-1. Control Bit Definition for Downstream Ports Control Bits Bit1 Bit 0 0 0 0 1 1 0 1 1 Control Action Not Forcing (Normal USB Function) Force Differential `1' (D+ HIGH, D- LOW) Force Differential `0' (D+ LOW, D- HIGH) Force SE0 state
An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 18-5) and Hub Ports Force High Register (Figure 18-6). With these registers the pins of the downstream ports can be individually forced LOW, or left unforced. Unlike the Hub Downstream Ports Control Register, above, the Force Low Register does not produce standard USB edge rate control on the forced pins. However, this register allows downstream port pins to be held LOW in suspend. This register can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification.
Hub Ports Force Low Bit # 7
6 Force Low D-[4] R/W 0
5 Force Low D+[3] R/W 0
4 Force Low D-[3] R/W 0
3 Force Low D+[2] R/W 0
2 Force Low D-[2] R/W 0
1 Force Low D+[1] R/W 0
ADDRESS 0
0x51
Bit Name Read/Write Reset
Force Low D+[4] R/W 0
Force Low D-[1] R/W 0
Figure 18-5. Hub Ports Force Low Register Hub Ports Force Low Bit # 7 Bit Name Read/Write Reset Reserved ADDRESS 0 Force Low D-[5] R/W 0 0x52
6 Reserved -
5 Force Low D+[7] R/W 0
4 Force Low D-[7] R/W 0
3 Force Low D+[6] R/W 0
2 Force Low D-[6] R/W 0
1 Force Low D+[5] R/W 0
Figure 18-6. Hub Ports Force Low Register
The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 18-7) and the Hub Ports Data Register (Figure 18-8). The data read from the Hub Ports Data Register is the differential data only and is independent of the settings of the Hub Ports Speed Register (Figure 18-2). When the SE0 condition is sensed on a downstream port, the corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status Register and Hub Ports Data Register are cleared upon reset or bus reset.
Hub Ports SE0 Status Bit # Bit Name Read/Write Reset 7 Reserved R 0 6 Port 7 SE0 Status R 0 5 Port 6 SE0 Status R 0 4 Port 5 SE0 Status R 0 3 Port 4 SE0 Status R 0 2 Port 3 SE0 Status R 0 1 Port 2 SE0 Status R 0 ADDRESS 0 Port 1 SE0 Status R 0 0x4F
Figure 18-7. Hub Ports SE0 Status Register
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Bit [0..6] : Port x SE0 Status (where x = 1..7) Set to 1 if a SE0 is output on the Port x bus; Set to 0 if a Non-SE0 is output on the Port x bus. Bit 7 : Reserved. Set to 0.
Hub Ports Data Bit # Bit Name Read/Write Reset 7 Reserved R 0 6 5 4 3 2 1 ADDRESS 0 0x50
Port 7 Diff. Data Port 6 Diff. Data Port 5 Diff. Data Port 4 Diff. Data Port 3 Diff. Data Port 2 Diff. Data Port 1 Diff. Data R 0 R 0 R 0 R 0 R 0 R 0 R 0
Figure 18-8. Hub Ports Data Register
Bit [0..6] : Port x Diff Data (where x = 1..7) Set to 1 if D+ > D- (forced differential 1, if signal is differential, i.e. not a SE0 or SE1). Set to 0 if D- > D+ (forced differential 0, if signal is differential, i.e., not a SE0 or SE1); Bit 7 : Reserved. Set to 0.
18.4
Downstream Port Suspend and Resume
The Hub Ports Suspend Register (Figure 18-9) and Hub Ports Resume Status Register (Figure 18-10) indicate the suspend and resume conditions on downstream ports. The suspend register must be set by firmware for any ports that are selectively suspended. Also, this register is only valid for ports that are selectively suspended. If a port is marked as selectively suspended, normal USB traffic is not sent to that port. Resume traffic is also prevented from going to that port, unless the Resume comes from the selectively suspended port. If a resume condition is detected on the port, hardware reflects a Resume back to the port, sets the Resume bit in the Hub Ports Resume Register, and generates a hub interrupt. If a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared. The Device Remote Wakeup bit (bit 7) of the Hub Ports Suspend Register controls whether or not the resume signal is propagated by the hub after a connect or a disconnect event. If the Device Remote Wakeup bit is set, the hub will automatically propagate the resume signal after a connect or a disconnect event. If the Device Remote Wakeup bit is cleared, the hub will not propagate the resume signal. The setting of the Device Remote Wakeup flag has no impact on the propagation of the resume signal after a downstream remote wakeup event. The hub will automatically propagate the resume signal after a remote wakeup event, regardless of the state of the Device Remote wakeup bit. The state of this bit has no impact on the generation of the hub interrupt. These registers are cleared on reset or bus reset. These registers are cleared on reset or USB bus reset.
Hub Ports Suspend Bit # Bit Name 7 6 5 Port 6 Selective Suspend R/W 0 4 Port 5 Selective Suspend R/W 0 3 Port 4 Selective Suspend R/W 0 2 Port 3 Selective Suspend R/W 0 1 Port 2 Selective Suspend R/W 0 Device Remote Port 7 Wakeup Selective Suspend R/W 0 R/W 0 ADDRESS 0 Port 1 Selective Suspend R/W 0 0x4D
Read/Write Reset
Figure 18-9. Hub Ports Suspend Register
Bit [0..6] : Port x Selective Suspend (where x = 1..7) Set to 1 if Port x is Selectively Suspended; Set to 0 if Port x Do not suspend. Bit 7 : Device Remote Wakeup. When set to 1, Enable hardware upstream resume signaling for connect/disconnect events during global resume. When set to 0, Disable hardware upstream resume signaling for connect/disconnect events during global resume.
Hub Ports Resume Bit # Bit Name Read/Write Reset 7 Reserved 0 6 Resume 7 R 0 5 Resume 6 R 0 4 Resume 5 R 0 3 Resume 4 R 0 2 Resume 3 R 0 1 Resume 2 R 0 ADDRESS 0 Resume 1 R 0 0x4E
Figure 18-10. Hub Ports Resume Status Register
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Bit [0..6] : Resume x (where x = 1..7) When set to 1 Port x requesting to be resumed (set by hardware); default state is 0; Bit 7 : Reserved. Set to 0. Resume from a selectively suspended port, with the hub not in suspend, typically involves these actions: 1. Hardware detects the Resume, drives a K to the port, and generates the hub interrupt. The corresponding bit in the Resume Status Register (0x4E) reads `1' in this case. 2. Firmware responds to hub interrupt, and reads register 0x4E to determine the source of the Resume. 3. Firmware begins driving K on the port for 10 ms or more through register 0x4B. 4. Firmware clears the Selective Suspend bit for the port (0x4D), which clears the Resume bit (0x4E). This ends the hardware-driven Resume, but the firmware-driven Resume continues. To prevent traffic being fed by the hub repeater to the port during or just after the Resume, firmware should disable this port. 5. Firmware drives a timed SE0 on the port for two low-speed bit times as appropriate. Note: Firmware must disable interrupts during this SE0 so the SE0 pulse isn't inadvertently lengthened and appears as a bus reset to the downstream device. 6. Firmware drives a J on the port for one low-speed bit time, then it idles the port. 7. Firmware re-enables the port. Resume when the hub is suspended typically involves these actions: 1. Hardware detects the Resume, drives a K on the upstream (which is then reflected to all downstream enabled ports), and generates the hub interrupt. 2. The part comes out of suspend and the clocks start. 3. Once the clocks are stable, firmware execution resumes. An internal counter ensures that this takes at least 1 ms. Firmware should check for Resume from any selectively suspended ports. If found, the Selective Suspend bit for the port should be cleared; no other action is necessary. 4. The Resume ends when the host stops sending K from upstream. Firmware should check for changes to the Enable and Connect Registers. If a port has become disabled but is still connected, an SE0 has been detected on the port. The port should be treated as having been reset, and should be reported to the host as newly connected. Firmware can choose to clear the Device Remote Wake-up bit (if set) to implement firmware timed states for port changes. All allowed port changes wake the part. Then, the part can use internal timing to determine whether to take action or return to suspend. If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events.
18.5
USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and Control Register, as shown in Figure 18-11. All bits in the register are cleared during reset.
USB Status and Control Bit # 7 Bit Name Read/Write Reset Endpoint Size R/W 0 6 5 4 D- Upstream R 0 3 Bus Activity R/W 0 2 Control Action Bit 2 R/W 0 1 Control Action Bit 1 R/W 0 ADDRESS 0 0x1F
Endpoint Mode D+ Upstream R/W 0 R 0
Control Action Bit 0 R/W 0
Figure 18-11. USB Status and Control Register
Bits[2..0] : Control Action Set to control action as per Table 18-2.The three control bits allow the upstream port to be driven manually by firmware. For normal USB operation, all of these bits must be cleared. Table 18-2 shows how the control bits affect the upstream port.
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Table 18-2. Control Bit Definition for Upstream Port Control Bits 000 001 010 011 100 101 110 111 Bit 3 : Bus Activity This is a "sticky" bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a `0' to the Bus Activity bit clears it, while writing a `1' preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it. Bits 4 and 5 : D- Upstream and D+ Upstream These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW. Bit 6 : Endpoint Mode This bit used to configure the number of USB endpoints. See Section 19.2 for a detailed description. Bit 7 : Endpoint Size This bit used to configure the number of USB endpoints. See Section 19.2 for a detailed description. The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2. Not Forcing (SIE Controls Driver) Force D+[0] HIGH, D-[0] LOW Force D+[0] LOW, D-[0] HIGH Force SE0; D+[0] LOW, D-[0] LOW Force D+[0] LOW, D-[0] LOW Force D+[0] HiZ, D-[0] LOW Force D+[0] LOW, D-[0] HiZ Force D+[0] HiZ, D-[0] HiZ Control Action
19.0
USB SIE Operation
The CY7C66x13 SIE supports operation as a single device or a compound device. This section describes the two device addresses, the configurable endpoints, and the endpoint function.
19.1
USB Device Addresses
The USB Controller provides two USB Device Address Registers: A (addressed at 0x10)and B (addressed at 0x40). Upon reset and under default conditions, Device A has three endpoints and Device B has two endpoints. The USB Device Address Register contents are cleared during a reset, setting the USB device addresses to zero and disabling these addresses. Figure 19-1 shows the format of the USB Address Registers.
USB Device Address (Device A, B) Bit # 7 6 Bit Name Device Address Enable R/W 0 Device Address Bit 6 R/W 0 5 Device Address Bit 5 R/W 0 4 Device Address Bit 4 R/W 0 3 Device Address Bit 3 R/W 0 2 Device Address Bit 2 R/W 0 ADDRESSES 1 Device Address Bit 1 R/W 0 0x10(A) and 0x40(B) 0 Device Address Bit 0 R/W 0
Read/Write Reset
Figure 19-1. USB Device Address Registers
Bits[6..0] :Device Address Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host. Bit 7: Device Address Enable Must be set by firmware before the SIE can respond to USB traffic to the Device Address.
19.2
USB Device Endpoints
The CY7C66x13 controller supports up to two addresses and five endpoints for communication with the host. The configuration of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (see Figure 18-11). Bit 7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in Table 19-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).
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Table 19-1. Memory Allocation for Endpoints USB Status And Control Register (0x1F) Bits [7, 6] [0,0] [1,0] [0,1] One USB Address: A (5 Endpoints) Label EPA4 EPA3 EPA2 EPA1 EPA0 Start Address 0xD8 0xE0 0xE8 0xF0 0xF8 Size 8 8 8 8 8 [1,1] One USB Address: A (5 Endpoints) Label EPA3 EPA4 EPA0 EPA1 EPA2 Start Address 0xA8 0xB0 0xB8 0xC0 0xE0 Size 8 8 8 32 32 Two USB Addresses: A (3 Two USB Addresses: A (3 Endpoints) & B (2 Endpoints) Endpoints) &B (2 Endpoints) Label EPB1 EPB0 EPA2 EPA1 EPA0 Start Address 0xD8 0xE0 0xE8 0xF0 0xF8 Size 8 8 8 8 8 Label EPB0 EPB1 EPA0 EPA1 EPA2 Start Address 0xA8 0xB0 0xB8 0xC0 0xE0 Size 8 8 8 32 32
When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
19.3
USB Control Endpoint Mode Registers
All USB devices are required to have a control endpoint 0 (EPA0 and EPB0) that is used to initialize and control each USB address. Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses. Endpoint 0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or OUT endpoints. The endpoint mode registers are cleared during reset. When USB Status And Control Register Bits [6,7] are set to [0,0] or [1,0], the endpoint zero EPA0 and EPB0 mode registers use the format shown in Figure 19-2.
USB Device Endpoint Zero Mode (A0, B0) Bit # Bit Name 7 Endpoint 0 SETUP Received R/W 0 6 Endpoint 0 IN Received R/W 0 5 Endpoint 0 OUT Received R/W 0 4 ACK 3 Mode Bit 3 2 Mode Bit 2 ADDRESSES 1 Mode Bit 1 0x12(A0) and 0x42(B0) 0 Mode Bit 0
Read/Write Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Figure 19-2. USB Device Endpoint Zero Mode Registers
Bits[3..0] : Mode These sets the mode which control how the control endpoint responds to traffic. Bit 4 : ACK This bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. Bit 5: Endpoint 0 OUT Received 1 = Token received is an OUT token. 0 = Token received is not an OUT token. This bit is set by the SIE to report the type of token received by the corresponding device address is an OUT token. The bit must be cleared by firmware as part of the USB processing. Bit 6: Endpoint 0 IN Received 1 = Token received is an IN token. 0 = Token received is not an IN token. This bit is set by the SIE to report the type of token received by the corresponding device address is an IN token. The bit must be cleared by firmware as part of the USB processing. Bit 7: Endpoint 0 SETUP Received 1 = Token received is a SETUP token. 0 = Token received is not a SETUP token. This bit is set ONLY by the SIE to report the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will clear it (set it to 0). The bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU should not clear this bit during this interval, and subsequently, until the CPU first does an IORD to this endpoint 0 mode register. The bit must be cleared by firmware as part of the USB processing. Note: In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non-control endpoint 3, and has the format for non-control endpoints shown in Figure 19-3.
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Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits, which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data... ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked when updated. The locking mechanism does not apply to the mode registers of other endpoints. Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies that the contents have changed as desired, and that the SIE has not updated these values. While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 19-1 for the appropriate endpoint zero memory locations. The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 18-1. Additional information on the mode bits can be found in Table 20-2 and Table 20-1. Note: The SIE offers an "Ack out - Status in" mode and not an "Ack out - Nak in" mode. Therefore, if following the status stage of a Control Write transfer a USB host were to immediately start the next transfer, the new Setup packet could override the data payload of the data stage of the previous Control Write.
19.4
USB Non-Control Endpoint Mode Registers
ADDRESSES 5 Reserved R/W 0 4 ACK R/W 0 3 Mode Bit 3 R/W 0 2 Mode Bit 2 R/W 0 1 Mode Bit 1 R/W 0 0x14, 0x16, 0x44 0 Mode Bit 0 R/W 0
The format of the non-control endpoint mode registers is shown in Figure 19-3.
USB Non-Control Device Endpoint Mode Bit # Bit Name Read/Write Reset 7 STALL R/W 0 6 Reserved R/W 0
Figure 19-3. USB Non-Control Device Endpoint Mode Registers
Bits[3..0] : Mode These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in Table 18-1. Bit 4 : ACK This bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. Bits[6..5] : Reserved Must be written zero during register writes. Bit 7 : STALL If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.
19.5
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown in Figure 19-4.
USB Endpoint Counter Bit # 7 Bit Name Read/Write Reset 6 5 Byte Count Bit 5 R/W 0 4 Byte Count Bit 4 R/W 0 3 Byte Count Bit 3 R/W 0 2 ADDRESSES 1 0x11, 0x13, 0x15, 0x41, 0x43 0 Byte Count Bit 0 R/W 0
Data 0/1 Toggle Data Valid R/W 0 R/W 0
Byte Count Bit 2 R/W 0
Byte Count Bit 1 R/W 0
Figure 19-4. USB Endpoint Counter Registers
Bits[5..0] : Byte Count These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or SETUP transactions, the count is updated by hardware to the number of data bytes received, plus two for the CRC bytes. Valid values are 2 to 34, inclusive.
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Bit 6 : Data Valid This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a zero. Bit 7 : Data 0/1 Toggle This bit selects the DATA packet's toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit. Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking mechanism does not apply to the count registers of other endpoints.
19.6
Endpoint Mode/Count Registers Update and Locking Mechanism
The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 19-5. Two time points, UPDATE and SETUP, are shown in the same figure. The following activities occur at each time point: SETUP: The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time. The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that register. UPDATE: 1. Endpoint Mode Register - All the bits are updated (except the SETUP bit of the endpoint 0 mode register). 2. Counter Registers - All bits are updated. 3. Interrupt - If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 20-2. 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier.
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1. IN Token
Host To Device Device To Host Host To Device
S Y N C
IN
A D D R
E N D P
C R C 5
S Y N C
D A T A 1/0
Data
C R C 16
S Y N C
A C K
Token Packet
Data Packet
Hand Shake Packet
Host To Device
Device To Host
UPDATE
S Y N C
IN
A D D R
E N D P
C R C 5
S Y N C
NAK/STALL
H O S T
Token Packet
Data Packet
UPDATE
2. OUT or SETUP Token without CRC error
Host To Device Host To Device Device To Host
S Y N C
O U T / Set up
A D D R
E N D P
C R C 5
S Y N C
D A T A 1/0
D E V I C E
Data
C R C 16
S Y N C
ACK, NAK, STAL
Hand Shake Packet
Token Packet
Data Packet
SETUP
UPDATE
3. OUT or SETUP Token with CRC error
Host To Device Host To Device
S Y N C
O U T / Set up
A D D R
E N D P
C R C 5
S Y N C
D A T A 1/0
Data
C R C 16
Token Packet
Data Packet
UPDATE only if FIFO is written
Figure 19-5. Token/Data Packet Flow Diagram
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20.0 USB Mode Tables
Mode Bits SETUP 0000 0001 0010 0011 0100 0101 0110 0111 1000 ignore
Table 20-1. USB Register Mode Encoding Mode Disable Nak In/Out Status Out Only Stall In/Out Ignore In/Out Isochronous Out Status In Only Isochronous In Nak Out Ack Out(STALL[4]=0) [4] Nak Out - Status In Ack Out - Status In Nak In Ack IN(STALL[4]=0) Ack IN(STALL[4]=1) IN ignore OUT ignore NAK check stall ignore always stall ignore NAK ACK stall NAK ACK ignore ignore ignore check check Comments Ignore all USB traffic to this endpoint Forced from Setup on Control endpoint, from modes other than 0000 For Control endpoints For Control endpoints For Control endpoints For Isochronous endpoints For Control Endpoints For Isochronous endpoints Is set by SIE on an ACK from mode 1001 (Ack Out) On issuance of an ACK this mode is changed by SIE to 1000 (NAK Out) Is set by SIE on an ACK from mode 1011 (Ack Out- Status In) On issuance of an ACK this mode is changed by SIE to 1010 (NAK Out - Status In) Is set by SIE on an ACK from mode 1101 (Ack In) On issuance of an ACK this mode is changed by SIE to 1100 (NAK In)
accept NAK accept stall accept stall accept ignore ignore ignore accept TX 0 BYte ignore ignore ignore ignore TX count ignore ignore ignore
1001 Ack Out(STALL =1) 1001 1010 1011 1100 1101 1101
accept TX 0 BYte accept TX 0 BYte ignore ignore ignore NAK TX count stall
Nak In - Status Out 1110 Ack In - Status Out Mode 1111
accept NAK accept TX Count
Is set by SIE on an ACK from mode 1111 (Ack In - Status Out) On issuance of an ACK this mode is changed by SIE to 1110 (NAK In - Status Out)
This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lower nibble (bits 0..3). The bit settings for different modes are covered in the column marked "Mode Bits." The Status IN and Status OUT represent the Status stage in the IN or OUT transfer involving the control endpoint. Mode Bits These column lists the encoding for different modes by setting Bits[3..0] of the Endpoint Mode register. This modes represents how the SIE responds to different tokens sent by the host to an endpoint. For instance, if the mode bits are set to "0001" (NAK IN/OUT), the SIE will respond with an * ACK on receiving a SETUP token from the host * NAK on receiving an OUT token from the host * NAK on receiving an IN token from the host Refer to section 13.0 for more information on SIE functioning. SETUP, IN, and OUT These columns shows the SIE's response to the host on receiving a SETUP, IN and OUT token depending on the mode set in the Endpoint Mode Register. A "Check" on the OUT token column, implies that on receiving an OUT token the SIE checks to see whether the OUT packet is of zero length and has a Data Toggle (DTOG) set to `1.' If the DTOG bit is set and the received OUT Packet has zero length, the OUT is ACKed to complete the transaction. If either of this condition is not met the SIE will respond with a STALLL or just ignore the transaction. A "TX Count" entry in the IN column implies that the SIE transmit the number of bytes specified in the Byte Count (bits 3..0 of the Endpoint Count Register) to the host in response to the IN token received.
Note: 4. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to section 19.4.
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A "TX0 Byte" entry in the IN column implies that the SIE transmit a zero length byte packet in response to the IN token received from the host. An "Ignore" in any of the columns means that the device will not send any handshake tokens (no ACK) to the host. An "Accept" in any of the columns means that the device will respond with an ACK to a valid SETUP transaction tot he host. Comments Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 19-1, the SIE will change the endpoint Mode Bits [3:0] to NAK IN-Status OUT mode (1110) after ACK'ing a valid status stage OUT token. The firmware needs to update the mode for the SIE to respond appropriately. See Table 18-1 for more details on what modes will be changed by the SIE. A disabled endpoint will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). Firmware normally enables the endpoint mode after a SetConfiguration request. Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs and OUTs). Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token. The control endpoint has three status bits for identifying the token type received (SETUP, IN, or OUT), but the endpoint must be placed in the correct mode to function as such. Non-Control endpoints should not be placed into modes that accept SETUPs. Note that most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110. Table 20-2. Decode Table for Table 20-3: "Details of Modes for Differing Traffic Conditions"
Properties of Incoming Packets
Changes to the Internal Register made by the SIE on receiving an incoming packet from the host
Interrupt
3
2
1
0
Token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
3
2
1
0
Response
Int
Byte Count (bits 0..5, Figure 17-4) Endpoint Mode encoding Received Token (SETUP/IN/OUT) Data Valid (bit 6, Figure 17-4) Data0/1 (bit7 Figure 17-4) PID Status Bits (Bit[7..5], Figure 17-2) Endpoint Mode bits Changed by the SIE SIE's Response to the Host
The validity of the received data The quality status of the DMA buffer The number of received bytes
Acknowledge phase completed
Legend:
TX : transmit RX : receive
UC : unchanged TX0 :Transmit 0 length packet
available for Control endpoint only x: don't care
The response of the SIE can be summarized as follows: 1. The SIE will only respond to valid transactions, and will ignore non-valid ones. 2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC. 3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking; 4. An IN will be ignored by an OUT configured endpoint and visa versa. 5. The IN and OUT PID status is updated at the end of a transaction. 6. The SETUP PID status is updated at the beginning of the Data packet phase.
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7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be done by the firmware only after the transaction is complete. This represents about a 1-s window in which the CPU is locked from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This read will of course unlock the register. So care must be taken not to overwrite the register elsewhere. Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) Properties of Incoming Packet Mode Bits token count buffer dval See Setup <= 10 data valid Table 16-1 See Setup > 10 junk x Table 16-1 See Setup x junk invalid Table 16-1 Properties of Incoming Packet Mode Bits token count buffer dval DISABLED 0000x x UC x Nak In/Out 0 0 0 1 Out x UC x 0 0 0 1 In x UC x Ignore In/Out 0 1 0 0 Out x UC x 0 1 0 0 In x UC x Stall In/Out 0 0 1 1 Out x UC x 0 0 1 1 In x UC x Properties of Incoming Packet Mode Bits token count buffer dval Normal Out/premature status In 1 0 1 1 Out <= 10 data valid 1 0 1 1 Out > 10 junk x 1 0 1 1 Out x junk invalid 1 0 1 1 In x UC x NAK Out/premature status In 1 0 1 0 Out <= 10 UC valid 1 0 1 0 Out > 10 UC x 1 0 1 0 Out x UC invalid 1 0 1 0 In x UC x Status In/extra Out 0 1 1 0 Out <= 10 UC valid 0 1 1 0 Out > 10 UC x 0 1 1 0 Out x UC invalid 0 1 1 0 In x UC x Properties of Incoming Packet Document #: 38-08024 Rev. *A SETUP (if accepting SETUPs) Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr updates 1 updates 1 UC UC 1 0 0 0 1 ACK yes updates updates updates 1 updates 0 updates 1 UC UC UC UC UC UC NoChange ignore NoChange ignore yes yes
DTOG UC UC UC UC UC UC UC
Changes made by SIE to Internal Registers and Mode Bits DVAL COUNT Setup In Out ACK Mode Bits Response Intr UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 UC UC UC UC UC UC UC UC UC UC NoChange ignore NoChange NAK NoChange NAK NoChange ignore NoChange ignore no yes yes no no
UC UC UC UC 1 UC NoChange Stall yes UC UC UC 1 UC UC NoChange Stall yes CONTROL WRITE Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr 1 updates UC updates updates UC 0 updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 1 1 1 UC 1 UC UC UC 1 UC UC 1 UC UC UC 1 1 010 NoChange NoChange NoChange NoChange NoChange NoChange NoChange ACK ignore ignore TX 0 NAK ignore ignore TX 0 yes yes yes yes yes no no yes yes no no yes
updates updates updates UC UC UC UC UC UC UC UC UC
UC UC UC UC 1 UC 0 0 1 1 Stall UC UC UC UC UC UC NoChange ignore UC UC UC UC UC UC NoChange ignore UC UC UC 1 UC 1 NoChange TX 0 CONTROL READ Changes made by SIE to Internal Registers and Mode Bits
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Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) (continued) Mode Bits token count buffer Normal In/premature status Out 1 1 1 1 Out 2 UC 1 1 1 1 Out 2 UC 1 1 1 1 Out !=2 UC 1 1 1 1 Out > 10 UC 1 1 1 1 Out x UC 1 1 1 1 In x UC Nak In/premature status Out 1 1 1 0 Out 2 UC 1 1 1 0 Out 2 UC 1 1 1 0 Out !=2 UC 1 1 1 0 Out > 10 UC 1 1 1 0 Out x UC 1 1 1 0 In x UC Status Out/extra In 0 0 1 0 Out 2 UC 0 0 1 0 Out 2 UC 0 0 1 0 Out !=2 UC 0 0 1 0 Out > 10 UC 0 0 1 0 Out x UC 0 0 1 0 In x UC dval valid valid valid x invalid x valid valid valid x invalid x valid valid valid x invalid x DTOG 1 0 updates UC UC UC 1 0 updates UC UC UC 1 0 updates UC UC UC DVAL COUNT Setup In 1 1 1 UC UC UC 1 1 1 UC UC UC updates UC updates UC updates UC UC UC UC UC UC UC updates UC updates UC updates UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC UC UC 1 Out ACK Mode Bits Response Intr 1 1 1 UC UC UC 1 1 1 UC UC UC 1 UC UC UC UC 1 1 UC UC UC UC UC NoChange 0 011 0 011 NoChange NoChange 1 110 NoChange 0 011 0 011 NoChange NoChange NoChange ACK Stall Stall ignore ignore ACK (back) ACK Stall Stall ignore ignore NAK yes yes yes no no yes yes yes yes no no yes yes yes yes no no yes
Properties of Incoming Packet Mode Bits token count buffer dval Normal Out/erroneous In 1 0 0 1 Out <= 10 data valid 1 0 0 1 Out > 10 junk x 1 0 0 1 Out x junk invalid 1 0 0 1 In x UC x
1 updates UC UC 1 1 NoChange ACK 1 updates UC UC 1 UC 0 0 1 1 Stall 1 updates UC UC 1 UC 0 0 1 1 Stall UC UC UC UC UC UC NoChange ignore UC UC UC 1 UC UC NoChange ignore UC UC UC 1 UC UC 0 0 1 1 Stall OUT ENDPOINT Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out ACK Mode Bits Response 1 updates UC updates updates UC 0 updates UC UC UC UC UC UC UC UC 1 1 1 UC 1 UC UC UC 1 000 NoChange NoChange NoChange ACK ignore ignore ignore (STALL[4] = 0) NoChange Stall (STALL[4] = 1) NAK ignore ignore ignore
Intr yes yes yes no
updates updates updates UC
1
0
01
In
x
UC
x
UC
UC
UC
UC
UC UC
UC
no
NAK Out/erroneous In 1 0 0 0 Out <= 10 1 0 0 0 Out > 10 1 0 0 0 Out x 1 0 0 0 In x Isochronous endpoint (Out) 0 1 0 1 Out x 0 1 0 1 In x
UC UC UC UC
valid x invalid x
UC UC UC UC
UC UC UC UC
UC UC UC UC
UC UC UC UC
UC UC UC UC
1 UC UC UC
UC UC UC UC
NoChange NoChange NoChange NoChange
yes no no no yes no
updates updates updates updates updates UC UC 1 1 NoChange RX UC x UC UC UC UC UC UC UC NoChange ignore IN ENDPOINT Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Normal In/erroneous Out 1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore
Intr no
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Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) (continued) (STALL[4] = 0) NoChange stall no (STALL[4] = 1) 1 1 0 0 ACK (back) yes NoChange ignore NoChange NAK NoChange ignore NoChange TX no yes no yes
1
1
01
Out
x
UC
x
UC
UC
UC
UC
UC UC
UC
1 1 0 1 In x NAK In/erroneous Out 1 1 0 0 Out x 1 1 0 0 In x Isochronous endpoint (In) 0 1 1 1 Out x 0 1 1 1 In x
UC UC UC UC UC
x x x x x
UC UC UC UC UC
UC UC UC UC UC
UC UC UC UC UC
UC UC UC UC UC
1
UC
1 UC UC UC UC
UC UC 1 UC UC UC 1 UC
21.0
Register Summary
Bit 6 P0.6 P1.6 P2.6 P3.6 Bit 5 P0.5 P1.5 P2.5 P3.5 P0.5 Intr Enable P1.5 Intr Enable P2.5 Intr Enable Reserve d Port 2 Config Bit 1 Reserve d Device Address A Bit 5 Bit 4 P0.4 P1.4 P2.4 P3.4 P0.4 Intr Enable P1.4 Intr Enable P2.4 Intr Enable Reserve d Port 2 Config Bit 0 Reserve d Device Address A Bit 4 Bit 3 P0.3 P1.3 P2.3 P3.3 P0.3 Intr Enable Reserve d P2.3 Intr Enable Reserve d Port 1 Config Bit 1 Reserve d Device Address A Bit 3 Bit 2 P0.2 P1.2 P2.2 P3.2 P0.2 Intr Enable P1.2 Intr Enable Reserve d Reserve d Port 1 Config Bit 0 Reserve d Device Address A Bit 2 Bit 1 P0.1 P1.1 P2.1 P3.1 P0.1 Intr Enable P1.1 Intr Enable Reserve d P3.1 Intr Enable Port 0 Config Bit 1 I2C Port Width Device Address A Bit 1 Bit 0 P0.0 P1.0 P2.0 P3.0 Read/Write Default/ /Both[5, 6, 7] Reset bbbbbbbb 1111111 1 bbbbbbbb 1111111 1 bbbbbbbb 1111111 1 bbbbbbbb 1111111 1 wwwwwww 000000 w 00 wwwwwww 000000 w 00 wwwwwww 000000 w 00 wwwwwww 000000 w 00 bbbbbbbb 000000 00
Addr ess Register Name Bit 7 0x00 Port 0 Data P0.7 0x01 Port 1 Data
Endpoint A0, AI HAPI GPIO CONFIGURATION PORTS 0, 1, 2 AND 3 and A2 Configuration I2C
P1.7 P2.7 P3.7
0x02 Port 2 Data 0x03 Port 3 Data 0x04 Port 0 Interrupt Enable 0x05 Port 1 Interrupt Enable 0x06 Port 2 Interrupt Enable 0x07 Port 3 Interrupt Enable 0x08 GPIO Configuration
P0.7 Intr P0.6 Intr Enable Enable P1.7 Intr P1.6 Intr Enable Enable P2.7 Intr P2.6 Intr Enable Enable Reserve Reserve d d Port 3 Port 3 Config Config Bit 1 Bit 0 0x09 HAPI/I2C Configu- I2C Reserve ration Position d 0x10 USB Device Device Device Address A Address Address A Enable A Bit 6
P0.0 Intr Enable P1.0 Intr Enable Reserve d P3.0 Intr Enable Port 0 Config Bit 0 Reserve bbbbbbbb 000000 d 00 Device bbbbbbbb 000000 Address 00 A Bit 0
Notes: 5. B: Read and Write. 6. W: Write. 7. R: Read.
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21.0 Register Summary (continued)
Bit 5 Bit 4 Byte Byte Count Count Bit 5 Bit 4 Endpoint Endpoint Endpoint ACK 0 0 0 OUT SETUP IN Receive Receive Receive d d d Data 0/1 Data Byte Byte Toggle Valid Count Count Bit 5 Bit 4 STALL ACK Data 0/1 Data Toggle Valid STALL Byte Count Bit 5 Bit 3 Byte Count Bit 3 Mode Bit 3 Bit 2 Byte Count Bit 2 Mode Bit 2 Bit 1 Byte Count Bit 1 Mode Bit 1 Read/Write Default/ Bit 0 /Both[5, 6, 7] Reset Byte bbbbbbbb 000000 Count 00 Bit 0 Mode Bit bbbbbbbb 000000 0 00
Addr ess Register Name Bit 7 Bit 6 0x11 EP A0 Counter Data 0/1 Data Register Toggle Valid 0x12 EP A0 Mode Register
Endpoint A0, AI AND A2 Configuration
0x13 EP A1 Counter Register 0x14 EP A1 Mode Register 0x15 EP A2 Counter Register 0x16 EP A2 Mode Register 0x1F USB Status and Control 0x20 Global Interrupt Enable
ENDPOINT B0, B1 CONFIGURATION
1.024-m 128-s USB Bus -bbbbbbb s Interrupt RESET Interrupt Enable Interrupt Enable Enable 0x21 Endpoint Interrupt Reserve Reserve Reserve EPA2 EPA1 EPA0 ---bbbbb Enable d d d Interrupt Interrupt Interrupt Enable Enable Enable 0x24 Timer (LSB) Timer Bit Timer Bit Timer Bit Timer Bit Timer Bit Timer Bit rrrrrrrr 7 6 5 2 1 0 0x25 Timer (MSB) Reserve Reserve Reserve Timer Bit Time Bit Timer Bit ----rrrr d d d 10 9 8 2C Control and 0x28 I MSTR Continue Xmit bbbbbbbb ARB Receive I2C Status Mode / Mode Lost/ d Stop Enable Busy Restart 0x29 I2C Data I2C Data I2C Data I2C Data I2C Data I2C Data I2C Data I2C Data I2C Data bbbbbbbb 7 6 5 4 3 2 1 0 0x40 USB Device Device Device Device Device Device Device Device Device bbbbbbbb Address B Address Address Address Address Address Address Address Address B Enable B B B B Bit 3 B B B Bit 0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 0x41 EP B0 Counter Data 0/1 Data Byte Byte Byte Byte Byte Byte bbbbbbbb Register Toggle Valid Count Bit Count Bit Count Bit Count Bit Count Bit Count Bit 5 4 3 2 1 0 0x42 EP B0 Mode Endpoint Endpoint Endpoint ACK Mode Bit Mode Bit Mode Bit Mode Bit bbbbbbbb Register 0 0 0 3 2 1 0 SETUP IN OUT Receive Receive Receive d d d 0x43 EP B1 Counter Data 0/1 Data Byte Byte Byte Byte Byte Byte bbbbbbbb Register Toggle Valid Count Count Count Count Count Count Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x44 EP B1 Mode STALL ACK Mode Bit Mode Bit Mode Bit Mode Bit bbbbbbbb Register 3 2 1 0
INTERRUPT
Endpoint Endpoint D+ Size Mode Upstrea m Reserve I2C GPIO d Interrupt Interrupt Enable Enable
Byte Count Bit 3 Mode Bit 3 Byte Byte Count Count Bit 4 Bit 3 ACK Mode Bit 3 D- Bus Upstrea Activity m Reserve USB d Hub Interrupt Enable EPB1 EPB0 Interrupt Interrupt Enable Enable Timer Bit Timer Bit 4 3 Reserve Timer Bit d 11 ACK Addr
USBCS
Byte Count Bit 2 Mode Bit 2 Byte Count Bit 2 Mode Bit 2 Control Bit 2
Byte Count Bit 1 Mode Bit 1 Byte Count Bit 1 Mode Bit 1 Control Bit 1
Byte Count Bit 0 Mode Bit 0 Byte Count Bit 0 Mode Bit 0 Control Bit 0
bbbbbbbb 000000 00 bbbbbbbb 000000 00 bbbbbbbb 000000 00 bbbbbbbb 000000 00 bbrrbbbb -0xx000 0 -000000 0
---0000 0 000000 00 ----0000 000000 00 xxxxxxx x 000000 00
I2C
TIMER
000000 00 000000 00
000000 00 000000 00
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21.0 Register Summary (continued)
Read/Write Default/ Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /Both[5, 6, 7] Reset Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 bbbbbbbb 000000 Connect Connect Connect Connect Connect Connect 00 Status Status Status Status Status Status Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 bbbbbbbb 000000 Enable Enable Enable Enable Enable Enable 00 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 bbbbbbbb 000000 Speed Speed Speed Speed Speed Speed 00 Port 3 Port 3 Port 2 Port 2 Port 1 Port 1 bbbbbbbb 000000 Control Control Control Control Control Control 00 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Port 7 Port 7 Port 6 Port 6 Port 5 Port 5 --bbbbbb --00000 Control Control Control Control Control Control 0 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 bbbbbbbb 000000 Selective Selective Selective Selective Selective Selective Selective 00 Suspend Suspend Suspend Suspend Suspend Suspend Suspend Resume Resume Resume Resume Resume Resume Resume -rrrrrrr 000000 7 6 5 4 3 2 1 00 Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 rrrrrrrr 000000 SE0 SE0 SE0 SE0 SE0 SE0 SE0 00 Status Status Status Status Status Status Status Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 rrrrrrrr 000000 Diff. Data Diff. Data Diff. Data Diff. Data Diff. Data Diff. Data Diff. Data 00 Force Force Force Force Force Force Force bbbbbbbb 000000 Low Low Low Low Low Low Low 00 D-[4] D+[3] D-[3] D+[2] D-[2] D+[1] D-[1] Reserve Force Force Force Force Force Force --bbbbbb 000000 d Low Low Low Low Low Low 00 D+[7] D-[7] D+[6] D-[6] D+[5] D-[5] WDR USB Bus Power-o Suspend Interrupt Reserve Run rbbbbrbb 000100 Reset n Reset Enable d 01 Interrupt Sense
HUB PORT CONTROL, STATUS, SUSPEND RESUME, SE0, FORCE LOW
Addr ess Register Name Bit 7 Bit 6 0x48 Hub Port Connect Reserve Port 7 Status d Connect Status 0x49 Hub Port Enable Reserve Port 7 d Enable 0x4A Hub Port Speed Reserve Port 7 d Speed 0x4B Hub Port Control Port 4 Port 4 (Ports 4:1) Control Control Bit 1 Bit 0 0x4C Hub Port Control Reserve Reserve (Ports 7:5) d d 0x4D Hub Port Suspend Device Remote Wakeup 0x4E Hub Port Resume Reserve Status d 0x4F Hub Port SE0 Reserve Status d 0x50 Hub Ports Data 0x51 Hub Port Force Low (Ports 4:1) 0x52 Hub Port Force Low (Ports 7:5) Reserve d Force Low D+[4] Reserve d
0xFF Process Status & IRQ Control Pending
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22.0 Sample Schematic
GND 3.3v Regulator OUT IN
2.2 uF Vref 1.5K (RUUP) Vbus 22x2(Rext) .01 uF .01 uF Vref 2.2 uF
USB-A Vbus DD+ GND
Vref
Vcc
USB-B Vbus DD+ GND SHELL Optional
D0D0+
22x8(Rext)
D1D1+ D2-
4.7nF 250 VAC
XTALO
USB-A Vbus DD+ GND
D2+ D3D3+ D4D4+
10M
6.000 MHz
XTALI GND GND Vpp
15K(x8) (RUDN)
USB-A Vbus DD+ GND
POWER MANAGEMENT
USB-A Vbus DD+ GND
Figure 22-1. Sample Schematic
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CY7C66013 CY7C66113
23.0 Absolute Maximum Ratings
Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ........ 0C to +70C Supply Voltage on VCC relative to VSS........... -0.5V to +7.0V DC Input Voltage................................. -0.5V to +VCC + 0.5V DC Voltage Applied to Outputs in High-Z State .................................... -0.5V to +VCC + 0.5V Power Dissipation .....................................................500 mW Static Discharge Voltage ..........................................> 2000V Latch-up Current ................................................... > 200 mA Max Output Sink Current into Port 0, 1, 2, 3, and DAC[1:0] Pins ..................................................... 60 mA Max Output Sink Current into DAC[7:2] Pins .............. 10 mA Max Output Source Current from Port 1, 2, 3, 4 ........ 30 mA
24.0
Electrical Characteristics
Description Reference Voltage Programming Voltage (disabled) VCC Operating Current Supply Current--Suspend Mode Vref Operating Current Input Leakage Current Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage External USB Series Resistor External Upstream USB Pull-up Resistor 0V < Vin < 3.3V In series with each USB pin 1.5 k 5%, D+ to VREG -10 19 1.425 14.25 0 2.8 28 8.0 All ports, LOW to HIGH edge All ports, HIGH to LOW edge 20% 2% No USB Traffic[8] Any pin | (D+)-(D-) | 0.2 0.8 0.8 2.5 2.0 20 10 21 1.575 15.75 100 3.6 0.3 44 24.0 40% 8% No GPIO source current 3.3V 5% Conditions Min. 3.15 -0.4 Max. 3.45 0.4 50 50 10 1 Unit V V mA A mA A V V V pF A W kW kW ms V V W k VCC VCC
Electrical Characteristics (Fosc = 6 MHz; Operating Temperature = 0 to 70C, VCC = 4.0V to 5.25V)
Parameter General VREF Vpp ICC ISB1 Iref Iil Vdi Vcm Vse Cin Ilo Rext RUUP RUDN tvccs VUOH VUOL ZO Rup VITH VH
USB Interface
External Downstream Pull-down Resistors 15 k 5%, downstream USB pins VCC Ramp Rate Static Output High Static Output Low USB Driver Output Impedance Pull-up Resistance (typical 14 k) Input Threshold Voltage Input Hysteresis Voltage Linear ramp 0V to VCC[9] 15 k 5% to Gnd 1.5 k 5% to VREF Including Rext Resistor
Power-on Reset USB Upstream/Downstream Port
General Purpose I/O (GPIO)
Notes: 8. Add 18 mA per driven USB cable (upstream or downstream). This is based on transitions every two full-speed bit times on average. 9. Power-on Reset occurs whenever the voltage on VCC is below approximately 2.5V.
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Electrical Characteristics (Fosc = 6 MHz; Operating Temperature = 0 to 70C, VCC = 4.0V to 5.25V) (continued)
Parameter VOL VOH Rup Isink0(0) Isink0(F) Isink1(0) Isink1(F) Irange Tratio IsinkDAC Ilin Description Port 0,1,2,3 Output Low Voltage Output High Voltage DAC Pull-up Resistance (typical 14 k) DAC[7:2] Sink Current (0) DAC[7:2] Sink Current (F) DAC[1:0] Sink Current (0) DAC[1:0] Sink Current (F) Programmed Isink Ratio: max/min Tracking Ratio DAC[1:0] to DAC[7:2] DAC Sink Current Differential Nonlinearity Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V[11] Vout = 2.0V DC DAC Port[12]
[10]
Conditions IOL = 3 mA IOL = 8 mA IOH = 1.9 mA (all ports 0,1,2,3)
Min.
Max. 0.4 2.0
Unit V V V
2.4 8.0 0.1 0.5 1.6 8 4 14 1.6 24.0 0.3 1.5 4.8 24 6 22 4.8 0.6
DAC Interface k mA mA mA mA
mA LSB
25.0
Switching Characteristics (fOSC = 6.0 MHz)
Description Clock Rate Clock Period Clock HIGH time Clock LOW time Signaling[13] Transition Rise Time Transition Fall Time Rise / Fall Time Matching; (tr/tf) Full Speed Date Rate Current Sink Response Time Read Pulse Width OE LOW to Data Valid[14, 15] OE HIGH to Data High-Z[15] 0 15 Time)[15] 5 15 0 8.192 50 14.336 OE LOW to Data_Ready Deasserted[14, 15] Write Strobe Width Data Valid to STB HIGH (Data Set-up STB LOW to Latch_Empty WDT Period STB HIGH to Data High-Z (Data Hold Time)[15] Deasserted[14, 15] 15 40 20 60 4 4 90 12 0.25% 0.8 20 20 111 ns ns % Mb/s s ns ns ns ns ns ns ns ns ms Min. 6 0.25% 166.25 0.45 tCYC 0.45 tCYC 167.08 Max. Unit MHz ns ns ns
Parameter Clock Source fOSC tcyc tCH tCL USB Full-speed trfs tffs trfmfs tdratefs DAC Interface tsink tRD tOED tOEZ tOEDR tWR tDSTB tSTBZ tSTBLE Timer Signals twatch HAPI Read Cycle Timing
HAPI Write Cycle Timing
Notes: 10. Irange: Isinkn(15)/ Isinkn(0) for the same pin. 11. Tratio = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed. 12. Ilin measured as largest step size vs. nominal according to measured full scale and zero programmed values. 13. Per Table 7-6 of revision 1.1 of USB specification. 14. For 25-pF load. 15. Assumes chip select CS is asserted (LOW).
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CY7C66013 CY7C66113
tCYC tCH
CLOCK
tCL Figure 25-1. Clock Timing tr
D+ 90% 10% D- 90% 10%
tr
Figure 25-2. USB Data Signal Timing Interrupt Generated Int
CS (P2.6, input) tRD OE (P2.5, input)
DATA (output) tOED STB (P2.4, input) DReadyPin (P2.3, output) (Shown for DRDY Polarity=0) Internal Write
D[23:0] tOEZ
tOEDR (Ready)
Internal Addr
Port0
Figure 25-3. HAPI Read by External Interface from USB Microcontroller
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CY7C66013 CY7C66113
Interrupt Generated Int
CS (P2.6, input) tWR STB (P2.4, input) tSTBZ DATA (input) D[23:0] tDSTB OE (P2.5, input) tSTBLE LEmptyPin (P2.2, output) (Shown for LEMPTY Polarity=0) Internal Read (not empty)
Internal Addr
Port0
Figure 25-4. HAPI Write by External Device to USB Microcontroller
26.0
Ordering Information
PROM Size 8 KB 8 KB 8 KB Package Name O48 P25 O56 Package Type 48-pin (300-Mil) SSOP 48-pin (600-Mil) PDIP 56-pin (300-Mil) SSOP Operating Range Commercial Commercial Commercial
Ordering Code CY7C66013-PVC CY7C66013-PC CY7C66113-PVC
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CY7C66013 CY7C66113
27.0 Package Diagrams
48-pin Shrunk Small Outline Package O48
51-85061-*C
56-pin Shrunk Small Outline Package O56
51-85062-*C
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27.0 Package Diagrams (continued)
48-pin (600-Mil) Molded DIP P25
51-85020-*A
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C66013 CY7C66113
Document History Page
Document Title: CY7C66013, CY7C66113 Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Document Number: 38-08024 REV. ** *A ECN NO. 114525 124768 Issue Date 3/27/02 03/20/03 Orig. of Change DSG MON Description of Change Change from Spec number: 38-00591 to 38-08024 Added register bit definitions. Added default bit state of each register. Corrected the Schematic (location of the pull-up on D+). Added register summary. Removed information on the availability of the part in PDIP package. Modified Table 20-1 and provided more explanation regarding locking/unlocking mechanism of the mode register. Removed any information regarding the speed detect bit in Hub Port Speed register being set by hardware.
Document #: 38-08024 Rev. *A
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